# Vaibhav_Tripathi

B.Tech, Electrical Engineering, Indian Institute of Technology, Kanpur, 2006<br>M.S, Electrical Engineering, Stanford University, 2009<br>Admitted to Ph.D. Candidacy: 2008-2009<br>**Email**: vaibhavt AT stanford DOT edu <br>

**Research**: *High speed and high resolution SAR ADC’s*

The successive approximation register (SAR) ADC architecture is attractive for integration in aggressively scaled CMOS, primarily since it does not rely on linear amplification blocks. This research focuses on exploring the SAR ADC architecture and aims to push the performance of SAR based A/D converters, targeting both high resolution (~12bits) and high speed (>150MHz) in 65nm CMOS technology. For these targeted specifications, we chose the two-step pipelined SAR architecture (see Fig. 1) because it employs only one linear gain element. This makes it power efficient compared to conventional multi-stage pipeline ADCs. Since the ADC is targeting 12 bit performance, the stage 1 switched-capacitor DAC (CDAC) has a large total capacitance (~ 1.5 pF), primarily limited by thermal noise. This DAC is a part of the high-speed SAR loop, which computes the frontend digital bits. Therefore, the large capacitance needs to be switched at the internal SAR frequency (high speed), which significantly increases the switching energy. Moreover, since stage 1 shares its conversion time with residue amplification (see timing diagram in Fig. 1), it has a reduced time for SAR operation, thereby limiting the overall ADC sampling frequency. In our prototype ADC, we propose the use of two switched-capacitor DACs in the ADC frontend to solve this particular problem.

The proposed ADC block diagram is shown in Fig. 2. The frontend employs two CDACs, one for SAR operation (DAC1) and the other for residue computation (DAC2). Since the SAR operation only needs to be accurate upto the front end resolution, DAC1 has a small total capacitance (not limited by thermal noise), which allows fast SAR A/D conversion (< 2 ns). The computed bits are fed into DAC2, which has a large noise limited capacitance (~ 12 bits) and calculates the required residue voltage out of the fast SAR loop. In addition, since the SAR operation is performed using DAC1 (small capacitance), the switching energy is low. Therefore the proposed architecture separates the high-speed ADC computation from low-noise residue generation and improves the ADC conversion speed while maintaining low power operation.

The ADC was designed and fabcricated in TSMC 65 nm CMOS process and measurement results will be presented in September in CICC 2014.<br>

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*Fig. 1 Pipelined SAR ADC with timing diagram. Fig. 2 Proposed two CDAC architecture showing 6 bit frontend and 8 bit backend.*