BSEE, Iowa State University, 2008<br>MSEE, Iowa State University, 2009<br>Admitted to Ph.D. Candidacy: 2009-2010

Research: High Speed Analog Filters and Equalizers<br>

As high-speed links push for higher and higher throughputs, the increasing baud rate and signal bandwidth make it challenging and costly to equalize entirely in digital domain. Because of this fact there are now opportunities to perform some of the equalization in the energy efficient analog domain. Recent publications (Momtaz et al., JSSC 2010) have implemented feed-forward equalizers (FFEs) but have relied heavily on area expensive inductors and high power circuits. In this project, we are building a FFE equalizer using only inverters and capacitors. It is highly efficient due to the class AB operation of the inverter transconductors. Also, there are a low number of parasitic nodes, which translates to high bandwidth with no need for inductive peaking.

To account for the process, voltage, and temperature variations, a novel switched capacitor master/slave biasing circuit has been designed to perform background calibration of the delay cells. Postlayout simulations have shown state of the art performance in terms of power and noise, as well as area. The design is being fabricated in a TSMC40 process and will be tested during the summer 2015.


Rboesch-researchsummary-July2014.pngEmail: rboesch@stanford.edu<br>