BSEE, University of Texas at Austin, 2006<br> MSEE, Stanford University, 2008<br>Admitted to Ph.D. Candidacy: 2007-2008

<br> Research: High Speed&nbsp;<i>Low Power A/D Converters for Nano-Scale CMOS Technology</i><br> High speed multi-gigahertz microprocessors are becoming ubiquitous in everyday applications. To push the CPU’s performance and speed to the limits, the need for massively parallel operations and serial I/O has become crucial. As a result, massive interleaving of high-speed, low-power, and small-area ADC’s of low to medium resolution has become a critical area of ADC research.&nbsp;From an architectural stand point, however, it is desirable to reduce these systems' interleaving factor to minimize overhead in clock and signal distribution, calibration of interleaving artifacts, digital data combining, and input capacitance. An excellent candidate able to deliver the desired performance is the traditional high-speed pipelined ADC. Different from classical approaches that involve power-hungry operational amplifiers, however, aggressive steps have been taken to drastically reduce power consumption while maintaining bandwidth improvements commensurate with scaling trends.&nbsp;To reduce switching and clocking power, a 65-nm Silicon-On-Insulator (SOI) technology has been used. Combined with low power techniques similar to dynamic amplification 1 and incomplete settling 2, our recent work advances the state-of-the-art of high-speed converters and achieves a measured performance of a 8-b 500 MS/s pipelined ADC with an effective resolution of 6.7 ENOB and power disippation of 5.1 mW from a 1.2 V supply.<br> <u><br></u> 1 J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2008, pp. 216-217. 2&nbsp;E. Iroaga and B. Murmann, “A 12b, 75MS/s Pipelined ADC Using Incomplete Settling,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2006, pp. 222-223. <br> &nbsp; Fig. 1 - ADC Architecture. &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; Fig. 2 - Die photo of recent work &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;Fig. 3 - Survey of Single-Channel ADCs (ENOB &gt; 5.5) from 1997-2011 <br> 1 Van der Plas, ISSCC '08<u></u> 2 Wei, ISSCC '11 3 Chung, VLSI Symp '11 <br> Email: rayn06 AT stanford DOT edu Homepage**: http://www.stanford.edu/~rayn06