BSEE, Seoul National University, 2000<br>MSEE, Stanford University, 2004<br>Admitted to Ph.D. Candidacy: 2005-2006

Research: Digital Compensation of Distortion in Continuous Time Sigma-Delta ADCs

Continuous time (CT) sigma-delta ADCs have evolved as a promising, more power efficient alternative to their switched capacitor counterparts. Nevertheless, CT sigma-delta ADCs still rely on precisely linear analog integrators; this tends to lower bound the achievable power dissipation. In this project, we explore the opportunity of digital cancellation of analog distortion errors in a CT sigma-delta modulator loop. With relaxed analog linearity specifications, the constituent integrators can be realized at lower power and potentially yield higher bandwidth, and the distortion errors of several percents can be corrected with a digital processor of moderate complexity. A calibration path is implemented by adding a low-power auxiliary ADC and measuring the correlation between the main ADC output and two paths. An LMS algorithm is then used to eliminate the distortion error. Another significant drawback of CT sigma-delta ADC is its high sensitivity to feedback DAC clock jitter. In the proposed architecture, this issue is addressed through a modified feedback DAC configuration. A prototype ADC was implemented in 65-nm CMOS. <br>

&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fig. 1 - ADC&nbsp;Architecture <br>

dhkimdie2.jpg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; Fig. 2 - Die Photo &nbsp;&nbsp; <br>


Email: kidhyun AT stanford DOT edu <br>