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Short Bio

Aldo Peña Perez was born in Queretaro, Mexico, in 1981. Received the B. Sc. degree on Electronics Engineering from the Technological Institute of Queretaro, Mexico, in 2004. Received the M. Sc. degree from the National Institute of Astrophysics, Optics and Electronics (INAOE), Puebla, Mexico, in 2006 and Ph. D. degree from the University of Pavia, Italy, in 2010. During his Ph.D., he was involved on development, design and testing of low-power high-resolution sigma delta modulators. From 2010 to 2011 he joined the Integrated Micro-Systems Laboratory of the University of Pavia as postdoctoral research fellow. During 2012-2013 he worked for STMicroelectronics, Milan, Italy as analog engineer at the Body and Audio Division (BAD). He is currently a postdoctoral researcher within the Murmann Mixed-Signal Group at Stanford University, Stanford, CA. His main research activities include mixed signal design, in particular low-voltage, low-power oversampled data converters and analog amplifiers. <br> <br>


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<br> Contact Information:<br><span style=“color: rgb(153, 51, 0);”>STANFORD UNIVERSITY</span> <br> Department of Electrical Engineering - Paul G. Allen Building <br>420 Via Palou, Allen-134. Stanford, CA 94305-4070, USA. <br>Phone: +1-650-289-8655 <br><span style=“color: rgb(0, 0, 255);”>em@il:</span><br><br>



&nbsp; &nbsp; Current trends in integrated circuits and transducer technologies have made it possible to develop ultrasound beamformers that acquire and process data at a sufficiently high rate to produce high quality, real-time volumetric (3-D) imagers using conventional 2-D arrays 1. Because a significant data set has to be collected and treated, a considerable reduction in the signal processing hardware becomes crucial for realization of such systems. Single-bit ΣΔ ADCs have received significant attention for the design of digital beamformers since greatly reduce the complexity of the front-end signal path and simplify the coherent processing in beam forming with improved timing accuracy. <br>&nbsp; &nbsp; On this project a 4×4 beamforming channel configuration is being integrated using a 28nm CMOS process. Due to the large dynamic range necessary for 3-D ultrasound beamformer, a discrete-time third-order noise-shaping ΣΔ modulator is targeted to preserve adequate signal-to-noise ratio. The modulator employs inverter-based amplifiers 2, which replace classical low-voltage OTA architectures due to their inherent advantages such as rail-to-rail operation, scalability with technology and capability to operate with very low supply voltages.

<br> References:

1 S. R. Freeman et. al., “Delta-Sigma Oversampled Ultrasound Beamformer with Dynamic Delays”, IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 46, No. 2, March 1999.

2 Y. Chae and G. Han, “Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator”, IEEE Journal of Solid-State Circuits, Vol. 44, No. 2, February 2009.<br>


3D Ultrasound SystemV3.jpg



&nbsp; &nbsp; The scanning tunneling microscopy (STM) is a type of electron microscope that shows three-dimensional images of a sample. Based on the electron tunneling effect, the STM works by scanning a very sharp microtip over a surface, providing an extraordinarily high resolution. The sharpness of the microtip (typically in the order of 10nm-50nm) is extremely important since its quality dramatically affects the reliability of the STM imaging process. The tip is usually fabricated by the “drop-off” method, which is based on the electrochemical etching technique 1. <br>&nbsp; &nbsp; The etching progress is monitored by a feedback control circuit, which immediately cut-off the etching current as the part of the material wire immersed in the electrolyte drops off due its own weight. Control circuits were designed and built for both direct current (DC) 2 and alternating current (AC) 3 etching, enabling the fabrication of different kind of metallic tips (i.e. gold, nickel, platinum-iridium, palladium, etc). <br>&nbsp; &nbsp; This project is focused on the design of an improved feedback control circuit, which operates in both AC and DC electrochemical etching. Behavioral simulation results show that the proposed architecture can control the fabricating process with cut-off times in the state-of-art (~100ns).

<br> References:

1 P. J. Bryant, H. S. Kim, Y. C. Zheng, and R. Yang, “Technique for Shaping Scanning Tunneling Microscope Tips”, Review of Scientific Instruments, Vol. 58, 1115, 1987.

2 Y. Nakamura, Y. Meta and K. Maeda, “A Reproducible Method to Fabricate Atomically Sharp Tips for Scanning Tunneling Microscopy”, Review of Scientific Instruments, Vol. 70, 3373, 1999.

3 M. Jobbins, A. Raigoza and S. Kandel, “Circuit design for direct current and alternating current electrochemical etching of scanning probe microscopy tips”, Review of Scientific Instruments, Vol. 83, 036105-1-3, 2012.


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&nbsp; &nbsp; This project explores the development of an electrochemical-sensing interface for the transduction of discrete electronic and vibrational modes of a molecular analyte in a high-background liquid environment, utilizing the electronic tunneling current as the transduction mechanism 1. Noise is used as a gating mechanism to control the kinetics of the charge transfer process, and operates the interface in a regime where there is minimal thermal dissipation of discretized mode information. In order to have an independent control of both interface voltage and voltage noise power, a three-electrode cell driven by a low-noise potentiostat is used. <br>&nbsp; &nbsp; The three-electrode cell consists of a working electrode (WE), a reference electrode (RE), and a counter electrode (CE). The working electrode (WE) makes contact with the analyte and serves as a surface on which the electrochemical reaction takes place. For many physical electrochemistry experiments, the WE is an “inert” material such as gold and assists the charge transfer process to and from the analyte. The RE is used in measuring the working electrode potential and it does not provide any current flow. The CE is an inert electrode that completes the cell circuit since provides all the current required for electrochemical reaction. <br>&nbsp; &nbsp; The potentiostat system 2 is the electronic instrument that controls the potential difference applied between the WE and the RE at a desired cell potential (VBIAS) by injecting the proper amount of current into CE 2. The current generated in the CE is fed to the signal conditioning circuit where it is processed for further operation and information extraction. <br>&nbsp; &nbsp; Recent efforts in our electronic instrumentation have mainly included the design of a very low noise buffer circuit, which will replace the amplifier-based buffer involved in the feedback loop of our custom potentiostat. The circuit features a common-drain configuration (called also source follower) and employs monolithic Junction Field Effect (JFET) transistors 3 to ensure high input impedance (~1TΩ) and very low noise performance (~2nV√Hz from measurement results).


3-Electrode Potentiostat V2.jpg

<br> References:

1 C. Gupta, R.M. Walker, R. Gharpuray, M. Shulaker, Z. Zhang, M. Javanmard, R.W. Davis, B. Murmann, R.T. Howe, “Electrochemical Quantum Tunneling for Electronic Detection and Characterization of Biological Toxins”, Micro- and Nanotechnology Sensors, Systems, and Applications IV, Proc. of SPIE, Vol. 8373, May 2012.

2 “Potentiostat Fundamentals”, Application Note-GAMRY Instruments.

3 LSK489 – Low Noise Low Capacitance Monolithic Dual N-channel JFET.

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1 V.R. Gonzalez-Diaz, A. Peña-Perez, and F. Maloberti, “Opamp gain compensation technique for continuous-time ΣΔ modulators”, IET Electronics Letters, Vol. 50, Issue 5, pp. 355-356, Feb. 2014.

2 A. Peña-Perez, V.R. Gonzalez-Diaz and F. Maloberti, “ Analog Sigma-Delta Modulation with Op-Amp Gain Compensation for Nanometer Technologies”, Journal of Analog Integrated Circuits and Signal Processing, Vol. 73, Issue 3, pp. 297-305, Sept. 2013.

3 A. Peña-Perez, E. Bonizzoni and F. Maloberti, “A 88 dB DR, 84 dB SNDR Very Low-Power Single Op-Amp Third-Order ΣΔ Modulator”, IEEE Journal of Solid-State Circuits, Vol. 49. No. 9, pp. 2107-2118, Sept. 2012.

4 E. Bonizzoni,A. Peña-Perez, H. Caracciolo, D. Stoppa, and F. Maloberti, “An Incremental ADC Sensor Interface with Input Switch-Less Integrator Featuring 220-nVrms Resolution with +/-30mV Input Range”, Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 389-392, Sept. 2012.

5 V.R. Gonzalez-Diaz, A. Peña-Perez and F. Maloberti, “Fractional Frequency Synthesizers with Low Order Time-Variant Digital Sigma-Delta Modulator”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 59, No. 5, pp. 969-978, May 2012.

6 A. Peña-Perez, E. Bonizzoni and F. Maloberti: “A 84dB SNDR 100kHz Bandwidth Low-Power Single Op-Amp Third-Order ΔΣ Modulator Consuming 140µW”; IEEE International Solid-State Circuits Conference - Digest of Technical Papers (ISSCC), pp. 477-478, Feb. 2011.

7 E. Bonizzoni, A. Peña-Perez, F. Maloberti and M. A. Garcia-Andrade: “Two Op-Amps Third-Order Sigma-Delta Modulator with 61-dB SNDR, 6-MHz Bandwidth and 6-mW Power Consumption”, Journal of Analog Integrated Circuits and Signal Processing, Vol. 66, Issue 3, pp. 381-388, March 2011.