Publications

2020

  • V. Kesler, B. Murmann, and H. T. Soh, “Going Beyond the Debye Length: Overcoming Charge Screening Limitations in Next-Generation Bioelectronic Sensors,” ACS Nano (in press, 2020)
  • B. Murmann, “Mixed-Signal Computing for Deep Neural Network Inference,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems. DOI
  • Wei-Hsiang Ho, Yi-Hsun Hsieh, B. Murmann, and Wei-Zen Chen, “A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4, DOI
  • S. Weinreich, D. Muratore, Y. Chae, T. McKay, and B. Murmann, “Implications of Finite Clock Transition Time for LPTV Circuit Analysis,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4, DOI
  • K. Ganesan, T. Flores, B. Le, D. Muratore, N. Patel, S. Mitra, B. Murmann, and D. Palanker, “Sensory Particles with Optical Telemetry,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4, DOI
  • J. Kwon, C. Lee, Y. Chae, and B. Murmann, “Design Considerations for External Compensation Approaches to OLED Display Degradation,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4, DOI
  • C. Zhu, E. Schell, M.-G. Kim, Z. Bao, and B. Murmann, “Wearable System Design Using Intrinsically Stretchable Transducers,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4, DOI
  • A. Gural, P. Nadeau, M. Tikekar, and B. Murmann, “Low-Rank Training of Deep Neural Networks for Emerging Memory Technology,” 2009.03887 [cs.LG], Sep. 2020. URL
  • O. E. Mattia, M. Sawaby, K. Zheng, A. Arbabian and B. Murmann, “A 10 Gbps Continuous-Time Linear Equalizer for mm-Wave Dielectric Waveguide Communication,” IEEE Solid-State Circuits Letters, vol. 3, pp. 266-269, Aug. 2020. DOI
  • N. Even-Chen, D.G. Muratore, S.D. Stavisky, L.R. Hochberg, J.M. Henderson, B. Murmann and K.V. Shenoy “Power-saving design opportunities for wireless intracortical brain–computer interfaces,” Nat. Biomed. Eng., Aug. 2020. DOI
  • A. A. Youssef, B. Murmann and H. Omran, “Analog IC Design Using Precomputed Lookup Tables: Challenges and Solutions,” in IEEE Access, Jul. 2020. DOI
  • P. Caragiulo, O.E. Mattia, A. Arbabian, and B. Murmann, “A Compact 14 GS/s 8-bit Switched-Capacitor DAC in 16 nm FinFET CMOS,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2020, pp. 1-2. DOI
  • G. Nyikayaramba and B. Murmann, “S-Parameter-Based Defect Localization for Ultrasonic Guided Wave SHM,” Aerospace, vol. 7, no. 3, 2020. DOI
  • E. Chai, M. Pilanci, and B. Murmann, “Separating the Effects of Batch Normalization on CNN Training Speed and Stability Using Classical Adaptive Filter Theory,” arXiv:2002.10674 [cs.NE], Feb. 2020. URL
  • O. Mattia and B. Murmann, “An 80 GS/s 5.5 ENOB Time-Interleaved Inverter-Based CMOS Track-and-Hold,” Electronics Letters, Jan. 2020. DOI
  • N. Hammler and B. Murmann, “Distortion Analysis of RC Integrators With Wideband Input Signals,” IEEE Trans. Circuits and Systems I, vol. 67, no. 1, pp. 12-22, Jan. 2020. DOI

2019

  • D.G. Muratore, P. Tandon, M. Wootters, E.J. Chichilnisky, S. Mitra and B. Murmann, “A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording,” IEEE Trans. on Biomedical Circuits and Systems, vol. 13, no. 6, pp. 1128-1140, Dec. 2019. DOI
  • D. Bankman, J. Messner, A. Gural and B. Murmann, “RRAM-Based In-Memory Computing for Embedded Deep Neural Networks,” Proc. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Nov. 2019, pp. 1511-1515. DOI
  • U. Kraft, F. Molina‐Lopez, D. Son, Z. Bao, and B. Murmann, “Ink Development and Printing of Conducting Polymers for Intrinsically Stretchable Interconnects and Circuits,” Adv. Electron. Mater., Nov. 2019, 1900681. DOI
  • C. Young, A. Omid-Zohoor, P. Lajevardi and B. Murmann, “A Data-Compressive 1.5/2.75-bit Log-Gradient QVGA Image Sensor With Multi-Scale Readout for Always-On Object Detection,” IEEE J. Solid-State Circuits, vol. 54, no. 11, pp. 2932-2946, Nov. 2019. DOI
  • C. Zhu, H. Wu, G. Nyikayaramba, Z. Bao and B. Murmann, “Intrinsically Stretchable Temperature Sensor Based on Organic Thin-Film Transistors,” IEEE Electron Device Letters, vol. 40, no. 10, pp. 1630-1633, Oct. 2019. DOI
  • N. Shah, P. Lajevardi, K. Wojciechowski, C. Lang, and B. Murmann, “An Energy Harvester Using Image Sensor Pixels With Cold Start and Over 96% MPPT Efficiency,” Proc. ESSCIRC, Cracow, Poland, Sep. 2019, pp. 207-210. DOI
  • N. Shah, P. Lajevardi, K. Wojciechowski, C. Lang, and B. Murmann, “An Energy Harvester Using Image Sensor Pixels With Cold Start and Over 96% MPPT Efficiency,” IEEE Solid-State Circuits Letters, vol. 2, no. 9, pp. 207-210, Sep. 2019. DOI
  • N. Hammler, A. Cathelin, P. Cathelin and B. Murmann, “A Spectrum-Sensing DPD Feedback Receiver With 30x Reduction in ADC Acquisition Bandwidth and Sample Rate,” IEEE Trans. Circuits and Systems I, vol. 66, no. 9, pp. 3340-3351, Sep. 2019. DOI
  • A. Yu, D. Bankman, K. Zheng and B. Murmann, “Understanding Metastability in SAR ADCs: Part II: Asynchronous,” IEEE Solid-State Circuits Magazine, vol. 11, no. 3, pp. 16-32, Summer 2019. DOI Matlab Code
  • S. Fischer, D. Muratore, S. Weinreich, A. Peña-Perez, R.M. Walker, C. Gupta, R.T. Howe and B. Murmann, “Low-Noise Integrated Potentiostat for Affinity-Free Protein Detection with 12 nV/rt-Hz at 30 Hz and 1.8 pArms Resolution,” IEEE Solid-State Circuits Letters, vol. 2, no. 6, Jun. 2019, pp. 41-44. DOI
  • D. Bankman, A. Yu, K. Zheng and B. Murmann, “Understanding Metastability in SAR ADCs: Part I: Synchronous,” IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 86-97, Spring 2019. DOI
  • A. Gural and B. Murmann, “Memory-Optimal Direct Convolutions for Maximizing Classification Accuracy in Embedded Applications,” International Conference on Machine Learning (ICML), Long Beach, CA, Jun. 2019. PDF
  • D.G. Muratore, P. Tandon, M. Wootters, E.J. Chichilnisky, S. Mitra and B. Murmann, “A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019, pp. 1-5. DOI
  • D. Villamizar, D. Battaglino, D.G. Muratore, R. Hoshyar and B. Murmann, “Sound Classification using Summary Statistics and N-Path Filtering,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019, pp. 1-5. DOI
  • S.A. Deka, D.M. Stipanović, B. Murmann, and C.J. Tomlin, “Long-Short Term Memory Neural Network Stability and Stabilization Using Linear Matrix Inequalities,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019, pp. 1-5. DOI
  • J. Xu, H.-C. Wu, C. Zhu, A. Ehrlich, L. Shaw, M. Nikolka, S. Wang, F. Molina-Lopez, X. Gu, S. Luo, D. Zhou, Y.-H. Kim, G.-J. N. Wang, K. Gu, V.R. Feig, S. Chen, Y. Kim, T. Katsumata, Y.-Q Zheng, H. Yan, J.W. Chung, J. Lopez, B. Murmann, and Z. Bao, “Multi-scale ordering in highly stretchable polymer semiconducting films,” Nature materials, Apr. 2019. DOI
  • B. Murmann, P. Caragiulo, and R. Smith, “High-Speed DACs for Millimeter Wave Digital Arrays in FinFET CMOS,” GOMACTech Conference, Albuquerque, NM, Mar. 2019. PDF
  • C. Young, A. Omid-Zohoor, P. Lajevardi, and B. Murmann, “A Data-Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection,” ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2019, pp. 98-100. DOI
  • K. Zheng, B. Murmann, H. Zhang and G. Zhang, “Partitioning of TX & RX Feedforward Equalizer for 112-Gbps Serial Links,” DesingCon, Santa Clara, CA, Jan. 2019.
  • D. Bankman, L. Yang, B. Moons, M. Verhelst and B. Murmann, “An Always-On 3.8 μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28 nm CMOS,” IEEE J. Solid-State Circuits, vol. 54, no. 1, pp. 158-172, Jan. 2019. DOI

2018

  • K. Zheng, Y. Frans, S.L. Ambatipudi, S. Asuncion, H.T. Reddy, K. Chang, and B. Murmann, “An Inverter-Based Analog Front-End for a 56 Gb/s PAM-4 Wireline Transceiver in 16 nm CMOS,” IEEE Solid-State Circuits Letters, vol. 1 , no. 12 , Dec. 2018. http://dx.doi.org/10.1109/LSSC.2019.2894933
  • S.A. Deka, D.M. Stipanović, B. Murmann and C.J. Tomlin, “Global Asymptotic Stability and Stabilization of Long Short-Term Memory Neural Networks with Constant Weights and Biases,” J. Optim. Theory Appl. (JOTA), Nov. 2018. http://doi.org/10.1007/s10957-018-1447-6
  • U. Kraft, T. Zaki, F. Letzkus, J.N. Burghartz, E. Weber, B. Murmann, and H. Klauk, “Low‐Voltage, High‐Frequency Organic Transistors and Unipolar and Complementary Ring Oscillators on Paper,” Advanced Electronic Materials, p. 1800453, Nov. 2018. http://doi.org/10.1002/aelm.201800453
  • W. Jiang, Y. Zhu, C.‐H. Chan, B. Murmann, S.‐P. U, and R.P. Martins, “7b 2 Gs/S Time‐Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler,” in Proc. IEEE Asian Solid-State Circuits Conf., Tainan, Taiwan, Nov. 2018.
  • S. Athreya, H. Hedayati, S. Kazemkhani, Y. Chen, S. Vats, M. Scott, B. Zeydel, P. Keller, J. Wang, B. Avula, B. Murmann, and E. Iroaga, “Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in a Multi-Lane Coherent Receiver,” Proc. ESSCIRC, Dresden, Germany, Sep. 2018, pp. 250-253. http://dx.doi.org/10.1109/ESSCIRC.2018.8494254
  • G. Hills, D. Bankman, B. Moons, L. Yang, J. Hillard, A.B. Kahng, R. Park, M. Verhelst, B. Murmann, M. Shulaker, H.-S.P. Wong, and S. Mitra, “TRIG: Hardware Accelerator for Inference-Based Applications and Experimental Demonstration Using Carbon Nanotube FETs,” Design Automation Conference (DAC), San Francisco, CA, Jun. 2018, pp. 1-10. http://dx.doi.org/10.1109/DAC.2018.8465852
  • K. Zheng, Y. Frans, S.L. Ambatipudi, S. Asuncion, H.T. Reddy, K. Chang, and B. Murmann, “An Inverter-based Analog Front End for a 56 Gb/s PAM4 Wireline Transceiver in 16nm CMOS,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2018, pp. 269-270. http://dx.doi.org/10.1109/VLSIC.2018.8502377
  • D.M. Stipanović, B. Murmann, M. Causo, A. Lekic, V.R. Royo, C.J. Tomlin, S. Thuries, M. Zarudnievz, and S. Lesecq, “Some Local Stability Properties of an Autonomous Long Short-Term Memory Neural Network Model,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018, pp. 1-5. http://dx.doi.org/10.1109/ISCAS.2018.8350958
  • M. Kwon and B. Murmann, “A New Figure of Merit Equation for Analog-to-Digital Converters in CMOS Image Sensors,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018, pp. 1-5. http://dx.doi.org/10.1109/ISCAS.2018.8351578
  • L. Yang, D. Bankman, B. Moons, M. Verhelst, and B. Murmann, “Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor,” in Proc. IEEE Int. Symp. Circuits Syst., Florence, Italy, May 2018, pp. 1-5. http://dx.doi.org/10.1109/ISCAS.2018.8351255
  • A. Omid-Zohoor, C. Young, D. Ta and B. Murmann, “Towards Always-On Mobile Object Detection: Energy vs. Performance Tradeoffs for Embedded HOG Feature Extraction,” IEEE Trans. Circuits and Systems for Video Technology, vol. 28, no. 5, pp. 1102-1115, May 2018. http://dx.doi.org/10.1109/TCSVT.2017.2653187
  • K. Zheng, Y. Frans, K. Chang, and B. Murmann, “A 56 Gb/s 6 mW 300 um2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS,” Proc. CICC, San Diego, CA, Apr. 2018. http://dx.doi.org/10.1109/CICC.2018.8357076
  • B. Moons, D. Bankman, L. Yang, B. Murmann, and M. Verhelst, “BinarEye: An Always-On Energy-Accuracy-Scalable Binary CNN Processor With All Memory On Chip In 28nm CMOS” Proc. CICC, San Diego, CA, Apr. 2018. http://dx.doi.org/10.1109/CICC.2018.8357071
  • C. Zhu, A. Chortos, Y. Wang, R. Pfattner, T. Lei, A.C. Hinckley, I. Pochorovski, X. Yan, J.W.-F. To, J.Y. Oh, J.B.-H. Tok, Z. Bao and B. Murmann, “Stretchable temperature-sensing circuits with strain suppression based on carbon nanotube transistors,” Nat. Electron., vol. 1, no. 3, pp. 183–190, 2018. http://dx.doi.org/10.1038/s41928-018-0041-0
  • S. Wang, J. Xu, W. Wang, G.-J. N. Wang, R. Rastak, F. Molina-Lopez, J.W. Chung, S. Niu, V.R. Feig, J. Lopez, T. Lei, S.-K. Kwon, Y. Kim, A.M. Foudeh, A. Ehrlich, A. Gasperini, Y. Yun, B. Murmann, J.B.-H. Tok and Z. Bao, “Skin electronics from scalable fabrication of an intrinsically stretchable transistor array,” Nature, Feb. 19, 2018 (online). http://dx.doi.org/10.1038/nature25494
  • D. Bankman, L. Yang, B. Moons, M. Verhelst and B. Murmann, “An Always-On 3.8μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28nm CMOS,” ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2018, pp. 222-223. http://dx.doi.org/10.1109/ISSCC.2018.8310264
  • K. Zheng, B. Murmann, H. Zhang and G. Zhang, “Feedforward Equalizer Location Study for High Speed Serial Systems,” DesingCon, Santa Clara, CA, Jan. 2018. http://designcon.com/paper-award-winners Best Paper Award.

2017

  • M-C. Chen, A. Peña Perez, S-R. Kothapalli, P. Cathelin, A. Cathelin, S.S. Gambhir, and B. Murmann, “A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI,” IEEE J. Solid-State Circuits, vol. 52, no. 11, pp. 2843-2856, Nov. 2017. http://dx.doi.org/10.1109/JSSC.2017.2749425
  • U. Kraft, F. Molina-Lopez, C. Zhu, Y. Wang, Z. Bao and B. Murmann, “Inkjet-printed, intrinsically stretchable conductors and interconnects,” Proc. SPIE Organic Photonics + Electronics, San Diego, CA, Aug. 2017. http://dx.doi.org/10.1117/12.2274583
  • A. Chortos, C. Zhu, J.Y. Oh, X. Yan, I. Pochorovski, J.W.F. To, N. Liu, U. Kraft, B. Murmann, and Z. Bao, “Investigating Limiting Factors in Stretchable All-Carbon Transistors for Reliable Stretchable Electronics,” ACS Nano, Jul. 2017. http://dx.doi.org/10.1021/acsnano.7b02458
  • L. Yang and B. Murmann, “Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, Jul. 2017, pp. 689-694. http://dx.doi.org/10.1109/ISVLSI.2017.117
  • D. Adams, Y.C. Eldar and B. Murmann, “A Mixer Frontend for a Four-Channel Modulated Wideband Converter with 62 dB Blocker Rejection,” IEEE J. Solid-State Circuits, vol. 52, no. 5, pp. 1286-1294, May 2017. http://dx.doi.org/10.1109/JSSC.2017.2647941
  • E. Lee, D. Miyashita, E. Chai, B. Murmann, S. Wong, “LogNet: Energy-efficient Neural Networks using Logarithmic Computation,” Proc. ICASSP, New Orleans, LA, Mar. 2017, pp. 5900-5904. http://dx.doi.org/10.1109/ICASSP.2017.7953288
  • L. Yang and B. Murmann, “SRAM voltage scaling for energy-efficient convolutional neural networks,” International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, Mar. 2017, pp. 7-12. http://dx.doi.org/10.1109/ISQED.2017.7918284
  • Y. Wang, C. Zhu, R. Pfattner, H. Yan, L. Jin, S. Chen, F. Molina-Lopez, F. Lissel, J. Liu, N. I. Rabiah, Z. Chen, J. W. Chung, C. Linder, M. F. Toney, B. Murmann and Z. Bao, “A highly stretchable, transparent, and conductive polymer,” Science Advances, vol. 3, no. 3, Mar. 2017 http://dx.doi.org/10.1126/sciadv.1602076
  • M-C. Chen, A. Peña Perez, S-R. Kothapalli, P. Cathelin, A. Cathelin, S.S. Gambhir, and B. Murmann, “A Pixel-Pitch-Matched Ultrasound Receiver for 3D Photoacoustic Imaging with Integrated Delta-Sigma Beamformer in 28nm UTBB FDSOI,” ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2017, pp. 456-457. http://dx.doi.org/10.1109/ISSCC.2017.7870458
  • M. Kramer, E. Janssen, K. Doris and B. Murmann, “A 14 bit, 30 MS/s, 38 mW SAR ADC Using Noise Filter Gear Shifting,” in IEEE Trans. on Ckt. Syst. II, vol. 64, no. 2, pp. 116-120, Feb. 2017. http://dx.doi.org/10.1109/TCSII.2016.2554858
  • J. Xu, S. Wang, Ging-Ji N. Wang, C. Zhu, S. Luo, L. Jin, X. Gu, S. Chen, V.R. Feig, J.W.F. To, S. Rondeau-Gagné, J. Park, B.C. Schroeder, C. Lu, J.Y. Oh, Y. Wang, Yun-Hi Kim, H. Yan, R. Sinclair, D. Zhou, Gi Xue, B. Murmann, C. Linder, W. Cai, J.B.-H. Tok, J.W. Chung, and Z. Bao, “Highly stretchable polymer semiconductor films through the nanoconfinement effect,” Science, vol. 355, no. 6320, pp. 59-64, Jan. 2017. http://dx.doi.org/10.1126/science.aah4496

2016

  • C. Gupta, Aldo Peña Perez, S.R. Fischer, S.B. Weinreich, B. Murmann, and R.T. Howe, “Active control of probability amplitudes in a mesoscale system via feedback-induced suppression of dissipation and noise,” Journal of Applied Physics, vol. 120, no. 22, Dec. 2016. http://dx.doi.org/10.1063/1.4971867
  • D. Bankman and B. Murmann, “An 8-Bit, 16 Input, 3.2 pJ/op Switched-Capacitor Dot Product Circuit in 28-nm FDSOI CMOS,” Proc. IEEE Asian Solid-State Circuits Conf., Toyama, Japan, Nov. 2016, pp. 21-24. http://dx.doi.org/10.1109/ASSCC.2016.7844125
  • Si Chen and B. Murmann, “An 8-Bit 1.25GS/S CMOS IF-Sampling ADC with Background Calibration for Dynamic Distortion,” Proc. IEEE Asian Solid-State Circuits Conf., Toyama, Japan, Nov. 2016, pp. 69-72. http://dx.doi.org/10.1109/ASSCC.2016.7844137
  • D. Robertson, A. Buchwald, M. Flynn, Hae-Seung Lee, Un-Ku Moon, and B. Murmann, “Data Converter Reflections: 19 Papers from the Last Ten Years That Deserve a Second Look,” Proc. ESSCIRC, Lausanne, Switzerland, Sep. 2016, pp. 161-164. http://dx.doi.org/10.1109/ESSCIRC.2016.7598267
  • R. Boesch, K. Zheng, and B. Murmann, “A 0.003 mm2 5.2 mW/tap 20 GBd Inductor-less 5-Tap Analog RX-FFE,” in Symp. VLSI Circuits Dig., Honolulu, HI, June 2016, pp. 170-171. http://dx.doi.org/10.1109/VLSIC.2016.7573522
  • D. Adams, Y.C. Eldar, and B. Murmann, “A Mixer Frontend for a Four-Channel Modulated Wideband Converter with 62 dB Blocker Rejection,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francsico, CA, May 2016, pp. 286-289. http://dx.doi.org/10.1109/RFIC.2016.7508307
  • T. Hoffmann, C. Fulton, M. Yeary, D. Thompson, A. Saunders, B. Murmann, B. Chen and A. Guo, “IMPACT - A Common Building Block to Enable Next Generation Radar Arrays,” IEEE Radar Conference, Philadelphia, PA, May 2016. http://dx.doi.org/10.1109/RADAR.2016.7485175
  • B. Murmann, “The successive approximation register ADC: a versatile building block for ultra-low-power to ultra-high-speed applications,” in IEEE Communications Magazine, vol. 54, no. 4, pp. 78-83, Apr. 2016. http://dx.doi.org/10.1109/MCOM.2016.7452270
  • D.J. Rogers and B. Murmann, “Digital active gate drives using sequential optimization,” IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, March 2016, pp. 1650-1656. http://dx.doi.org/10.1109/APEC.2016.7468088
  • D. Miyashita, E.H. Lee, and B. Murmann, “Convolutional Neural Networks using Logarithmic Data Representation,” arXiv:1603.01025 [cs.NE], March 2016. http://arxiv.org/abs/1603.01025

2015

  • M. Krämer, E. Janssen, K. Doris, and B. Murmann, “A 14b 35MS/s SAR ADC Achieving 75dB SNDR and 99dB SFDR with Loop-Embedded Input Buffer in 40nm CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 12, pp. 2891-2900, Dec. 2015. http://dx.doi.org/10.1109/JSSC.2015.2463110
  • M. Saadat and B. Murmann, “A 0.6V - 2.4V Input, Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter for Energy Harvesting Sensor Tags,” in Proc. IEEE Asian Solid-State Circuits Conf., Xiamen, China, Nov. 2015. http://dx.doi.org/10.1109/ASSCC.2015.7387490
  • B. Murmann, D. Bankman, E. Chai, D. Miyashita, and L. Yang, “Mixed-Signal Circuits for Embedded Machine-Learning Applications,” Asilomar Conference on Signals, Systems and Computers, Asilomar, CA, Nov. 2015. http://dx.doi.org/10.1109/ACSSC.2015.7421361
  • J. Spaulding, Y.C. Eldar, and B. Murmann, “A sub-nyquist analog front-end with subarray beamforming for ultrasound imaging,” Proc. IEEE International Ultrasonics Symp., Taipei, Taiwan, Oct. 2015. http://dx.doi.org/10.1109/ULTSYM.2015.0324
  • B. Murmann, “The Race for the Extra Decibel: A Brief Review of Current ADC Performance Trajectories,” IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 58-66, 2015. http://dx.doi.org/10.1109/MSSC.2015.2442393
  • P.G.A. Jespers and B. Murmann, “Calculation of MOSFET Distortion Using the Transconductance-to-Current Ratio (gm/ID),” in Proc. IEEE Int. Symp. Circuits Syst., Lisbon, Portugal, May 2015, pp. 529-532. http://dx.doi.org/10.1109/ISCAS.2015.7168687
  • J. Spaulding, Y.C. Eldar, and B. Murmann, “Mixer-Based Subarray Beamforming for Sub-Nyquist Sampling Ultrasound Architectures,” Proc. ICASSP, Brisbane, Australia, Apr. 2015, pp. 882-886. http://dx.doi.org/10.1109/ICASSP.2015.7178096
  • L. Paulsen, T. Hoffmann, C. Fulton, M. Yeary, A. Saunders, D. Thompson, B. Chen, A. Guo, and B. Murmann, “Impact: A low cost reconfigurable digital beamforming common module building block for next generation phased arrays,” Proc. SPIE DSS, Baltimore, MD, Apr. 2015. http://dx.doi.org/10.1117/12.2179712
  • D. Bankman and B. Murmann, “Passive charge redistribution digital-to-analogue multiplier,” Electronics Letters, vol. 51, no. 5, pp. 386-388, March 5 2015. http://dx.doi.org/10.1049/el.2014.3995
  • M. Krämer, E. Janssen, K. Doris, and B. Murmann, “A 14b 35MS/s SAR ADC Achieving 75dB SNDR and 99dB SFDR with Loop-Embedded Input Buffer in 40nm CMOS,” ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2015, pp. 284-285. http://dx.doi.org/10.1109/ISSCC.2015.7063037
  • I. Vaisband, M. Saadat, and B. Murmann, “A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications,” IEEE Trans. Circuits Syst. I, vol. 62, no. 2, pp. 385-394, Feb. 2015. http://dx.doi.org/10.1109/TCSI.2014.2362971

2014

  • O. Zabroda and B. Murmann, “Eliminating Complex Conjugate Poles in Two-Stage Operational Amplifiers with Current Buffer Miller Compensation,” Analog Integrated Circuits and Signal Processing, Sep. 2014. http://dx.doi.org/10.1007/s10470-014-0395-9
  • J. Foster, P. Nuyujukian, O. Freifeld, H. Gao, R. Walker, S. Ryu, T. Meng, B. Murmann, M. Black, and K. Shenoy, “A freely-moving monkey treadmill model,” Journal of Neural Engineering, vol. 11, no. 4, Jul. 2014. http://dx.doi.org/10.1088/1741-2560/11/4/046020
  • Y. Guo, C. Aquino, D. Zhang, and B. Murmann, “A Four-Channel, +/- 36 V, 780 kHz Piezo Driver Chip for Structural Health Monitoring,” IEEE J. Solid-State Circuits, vol. 49, no. 7, pp. 1506–1513, Jul. 2014. http://dx.doi.org/10.1109/JSSC.2014.2315615
  • N. Hammler, Y.C. Eldar and B. Murmann, “Low-Rate Identification of Memory Polynomials,” Proc. IEEE Int. Symp. Circuits Syst., Melbourne, Australia, June 2014, pp. 1034-1037. http://dx.doi.org/10.1109/ISCAS.2014.6865315
  • S. Seth and B. Murmann, “Design and Optimization of Continuous-Time Filters Using Geometric Programming,” Proc. IEEE Int. Symp. Circuits Syst., Melbourne, Australia, June 2014, pp. 2089-2092. http://dx.doi.org/10.1109/ISCAS.2014.6865578
  • U. Zschieschang, R. Rodel, U. Kraft, K. Takimiya, T. Zaki, F. Letzkus, J. Butschke, H. Richter, J.N. Burghartz, W. Xiong, B. Murmann, and H. Klauk, “Low-voltage organic transistors for flexible electronics,” Proc. DATE, Dresden, Germany, March 2014, pp. 1-6. http://dl.acm.org/citation.cfm?id=2617047
  • S. Medawar, B. Murmann, P. Handel, N. Bjorsell, and M. Jansson, “Static Integral Nonlinearity Modeling and Calibration of Measured and Synthetic Pipeline Analog-Digital Converters,” IEEE Trans. Instrum. Meas., vol. 63, no. 3, pp. 502-511, March 2014. http://dx.doi.org/10.1109/TIM.2013.2282002

2013

  • Y. Guo, C. Aquino, D. Zhang, and B. Murmann, “A Four-Channel, ±36 V, 780 kHz Piezo Driver Chip for Structural Health Monitoring,” Proc. ESSCIRC, Bucharest, Romania, Sep. 2013, pp. 85-88. http://dx.doi.org/10.1109/ESSCIRC.2013.6649078
  • Y. Guo, C. Aquino, D. Zhang and B. Murmann, “Integrated Piezo-Element Drive Electronics for Structural Health Monitoring,” 9th International Workshop on Structural Health Monitoring (IWSHM), Stanford, CA, Sep. 2013. http://structure.stanford.edu/workshop/
  • S. Medawar, P. Händel, B. Murmann, N. Björsell, and M. Jansson, “Dynamic Calibration of Undersampled Pipelined ADCs by Frequency Domain Filtering,” IEEE Trans. Instrum. Meas., vol. 62, no. 7, pp. 1882-1891, July 2013. http://dx.doi.org/10.1109/TIM.2013.2248289
  • S. Seth and B. Murmann, “Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier,” IEEE Trans. Circuits Syst. I, vol. 60, no. 5, pp. 1168-1174, May 2013. http://dx.doi.org/10.1109/TCSI.2013.2244325
  • D.A. Hall, R.S. Gaster, K.A.A. Makinwa, S.X. Wang, and B. Murmann, “A 256 Pixel Magnetoresistive Biosensor Microarray in 0.18 µm CMOS,” IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1290-1301, May 2013. http://dx.doi.org/10.1109/JSSC.2013.2245058
  • P. Lajevardi, V.P. Petkov, and B. Murmann, “A ΣΔ Interface for MEMS Accelerometers using Electrostatic Spring-Constant Modulation for Cancellation of Bondwire Capacitance Drift,” IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 265-275, Jan. 2013. http://dx.doi.org/10.1109/JSSC.2012.2218721

2012

  • S. Seth, S. Wang, T. Kenny and B. Murmann, “A -131-dBc/Hz, 20-MHz MEMS Oscillator with a 6.9-mW, 69-kOhm, Gain-Tunable CMOS TIA,” Proc. ESSCIRC, Bordeaux, France, Sep. 2012, pp. 249-252. http://dx.doi.org/10.1109/ESSCIRC.2012.6341332
  • J. Kim and B. Murmann, “A 12-bit, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration,” IEEE J. Solid-State Circuits, vol. 47, no. 9, pp. 2141-2151, Sep. 2012. http://dx.doi.org/10.1109/JSSC.2012.2194191
  • Y. Chung, O. Johnson, M. Deal, Y. Nishi, B. Murmann, and Z. Bao, “Engineering the metal gate electrode for controlling the threshold voltage of organic transistors,” Appl. Phys. Lett., vol. 101, p. 063304 (4 pages), Aug. 2012. http://dx.doi.org/10.1063/1.4739511
  • S. Seth and B. Murmann, “Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier,” Proc. IEEE Int. Symp. Circuits Syst., Seoul, Korea, May, 2012, pp. 205-208. http://dx.doi.org/10.1109/ISCAS.2012.6271684
  • C. Gupta, R.M. Walker, R. Gharpuray, M.M. Shulaker, Z. Zhang, M. Javanmard, R.W. Davis, B. Murmann, and R.T. Howe, “Electrochemical quantum tunneling for electronic detection and characterization of biological toxins,” Proc. SPIE 8373, Micro- and Nanotechnology Sensors, Systems, and Applications IV, 837303, May 2012. http://dx.doi.org/10.1117/12.920692
  • H. Gao, R.M. Walker, P. Nuyujukian, K.A.A. Makinwa, K.V. Shenoy, B. Murmann and T.H. Meng, “HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 1043-1055, Apr. 2012. http://dx.doi.org/10.1109/JSSC.2012.2185338
  • D. Adams, C.S. Park, Y.C. Eldar, and B. Murmann, “Towards an Integrated Circuit Design of a Compressed Sampling Wireless Receiver,” Proc. ICASSP, Kyoto, Japan, Mar. 2012, pp. 5305-5308. http://dx.doi.org/10.1109/ICASSP.2012.6289118
  • A. Abusleme, A. Dragone, G. Haller and and B. Murmann, “Mismatch of lateral field Metal-Oxide-Metal Capacitors in a 180-nm CMOS Process,” Electronics Letters, vol. 48, no. 5, pp. 286-287, Mar. 1 2012. http://dx.doi.org/10.1049/el.2011.3804
  • P. Lajevardi, V.P. Petkov, and B. Murmann, “A ΣΔ Interface for MEMS Accelerometers using Electrostatic Spring-Constant Modulation for Cancellation of Bondwire Capacitance Drift,” ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2012, pp. 196-197. http://dx.doi.org/10.1109/ISSCC.2012.6176972
  • J. Jeon, B.C.-K. Tee, B. Murmann, and Z. Bao, “Micro-imprinted prism substrate for self-aligned short channel organic transistors on a flexible substrate,” Appl. Phys. Lett., vol. 100, p. 043301 (4 pages), Jan. 2012. http://dx.doi.org/10.1063/1.3679119

2011

  • R. Nguyen, C. Raynaud, A. Cathelin, and B. Murmann, “A 6.7-ENOB, 500-MS/s, 5.1-mW Dynamic Pipeline ADC in 65-nm SOI CMOS,” Proc. ESSCIRC, Helsinki, Finland, Sep. 2011, pp. 359-362. http://dx.doi.org/10.1109/ESSCIRC.2011.6044981
  • Y. Guo and B. Murmann, “Integrated Piezo-element Drive Electronics for Structural Health Monitoring,” Proc. 8th International Workshop on Structural Health Monitoring (IWSHM), Stanford, CA, Sep. 2011, pp. 1724–1731. http://structure.stanford.edu/workshop/proceedings.html
  • M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838-847, Apr. 2011. http://dx.doi.org/10.1109/JSSC.2011.2108125
  • Y. Chung, E. Verploegen, A. Vailionis, Y. Sun, Y. Nishi, B. Murmann, and Z. Bao, “Controlling Electric Dipoles in Nanodielectrics and its Applications for Enabling Air-Stable n-Channel Organic Transistors,” Nano Letters, vol. 11, no. 3, pp. 1161-1165, Mar. 2011. http://dx.doi.org/10.1021/nl104087u
  • T. Konishi, K. Inazu, J.G. Lee, M. Natsui, S. Masui, and B. Murmann, “Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology,” IEICE Trans. Electronics, vol. E94-C, no. 3, pp. 334-345, Mar. 2011. http://dx.doi.org/10.1587/transele.E94.C.334
  • S. Hori and B. Murmann, “Feedforward Interference Cancellation Architecture for Short-Range Wireless Communication,” IEEE Trans. Circuits Syst. II, vol. 58, no. 1, pp. 16-20, Jan. 2011. http://dx.doi.org/10.1109/TCSII.2010.2092828

2010

  • C. Daigle, A. Dastgheib, and B. Murmann, “A 12-bit 800-MS/s switched-capacitor DAC with open-loop output driver and digital predistortion,” in Proc. IEEE Asian Solid State Circuits Conf., Nov. 2010, pp. 1-4. http://dx.doi.org/10.1109/ASSCC.2010.5716580
  • J. Jeon, B. Murmann, and Z. Bao, “Full-Swing and High-Gain Pentacene Logic Circuits on Plastic Substrate,” IEEE Electron Device Letters, vol. 31, no. 12, pp. 1488-1490, Nov. 2010. http://dx.doi.org/10.1109/LED.2010.2081336
  • J. Kim and B. Murmann, “A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration,” in Proc. ESSCIRC, Sevilla, Spain, Sep. 2010, pp. 378-381. http://dx.doi.org/10.1109/ESSCIRC.2010.5619722
  • W. Xiong, Y. Guo, U. Zschieschang, H. Klauk, and B. Murmann, “A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass,” IEEE J. Solid-State Circuits, vol. 45, no. 7, pp. 1380-1388, Jul. 2010. http://dx.doi.org/10.1109/JSSC.2010.2048083
  • M. El-Chammas and B. Murmann, “A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2010, pp. 157-158. http://dx.doi.org/10.1109/VLSIC.2010.5560315
  • R. Nguyen and B. Murmann, “The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter,” IEEE Trans. Circuits Syst. I, vol. 57, no. 6, pp. 1244-1254, Jun. 2010. http://dx.doi.org/10.1109/TCSI.2009.2031763
  • D.A. Hall, R.S. Gaster, S.X. Wang, and B. Murmann, “Portable biomarker detection with magnetic nanotags,” in Proc. IEEE Int. Symp. Circuits Syst., Paris, France, May 2010, pp. 1779-1782. http://dx.doi.org/10.1109/ISCAS.2010.5537639
  • D. Hall, R. Gaster, S. Osterfeld, B. Murmann, and S. Wang, “GMR biosensor arrays: Correction techniques for reproducibility and enhanced sensitivity,” Biosensors and Bioelectronics, vol. 25, no. 9, pp. 2177-2181, May 2010. http://dx.doi.org/10.1016/j.bios.2010.01.039
  • D. Hall, R. Gaster, T. Lin, S. Osterfeld, S. Han, B. Murmann, and S. Wang, “GMR biosensor arrays: A system perspective,” Biosensors and Bioelectronics, vol. 25, no. 9, pp. 2051-2057, May 2010. http://dx.doi.org/10.1016/j.bios.2010.01.038
  • Y. Chung, B. Murmann, S. Selvarasah, M.R. Dokmeci, and Z. Bao, “Low-voltage and short-channel pentacene field-effect transistors with top-contact geometry using parylene-C shadow masks,” Appl. Phys. Lett., vol. 96, no. 13, p. 133306 (3 pages), Mar. 2010. http://dx.doi.org/10.1063/1.3336009
  • W. Xiong, U. Zschieschang, H. Klauk, and B. Murmann, “A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glass,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2010, pp. 134-135. http://dx.doi.org/10.1109/ISSCC.2010.5434017

2009

  • R.S. Gaster, D.A. Hall, C.H. Nielsen, S.J. Osterfeld, H. Yu, K.E. Mach, R.J. Wilson, B. Murmann, J.C. Liao, S.S. Gambhir, and S.X. Wang, “Matrix-insensitive protein assays push the limits of biosensors in medicine,” Nature Medicine, vol. 15, no. 11, pp. 1327-1332, Nov. 2009. http://dx.doi.org/10.1038/nm.2032
  • W. Xiong, Y. Guo, U. Zschieschang, H. Klauk, and B. Murmann, “A 3-V, 6-bit C-2C digital-to-analog converter using complementary organic thin-film transistors on glass,” in Proc. ESSCIRC, Athens, Greece, Sep. 2009, pp. 212-215. http://dx.doi.org/10.1109/ESSCIRC.2009.5326008
  • J. Salvia, P. Lajevardi, M. Hekmat, and B. Murmann, “A 56MΩ CMOS TIA for MEMS applications,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2009, pp. 199-202. http://dx.doi.org/10.1109/CICC.2009.5280878
  • P. Nikaeen and B. Murmann, “Digital Compensation of Dynamic Acquisition Errors at the Front-End of High-Performance A/D Converters,” IEEE J. Selected Topics in Signal Processing, vol. 3, no. 3, pp. 499-508, Jun. 2009. http://dx.doi.org/10.1109/JSTSP.2009.2020575
  • M. El-Chammas and B. Murmann, “General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs,” IEEE Trans. Circuits Syst. I, vol. 56, no. 5, pp. 902-910, May 2009. http://dx.doi.org/10.1109/TCSI.2009.2015206
  • J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1057-1066, Apr. 2009. http://dx.doi.org/10.1109/JSSC.2009.2014705
  • T. Sundstrom, B. Murmann, and C. Svensson, “Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters,” IEEE Trans. Circuits Syst. I, vol. 56, no. 3, pp. 509-518, Mar. 2009. http://dx.doi.org/10.1109/TCSI.2008.2002548
  • J. Salvia, R. Melamud, S. Chandorkar, H. Lee, Y. Qu, S. Lord, B. Murmann, and T. Kenny, “Phase Lock Loop based Temperature Compensation for MEMS Oscillators,” in Proc. IEEE MEMS, Sorrento, Italy, Jan. 2009, pp. 661-664. http://dx.doi.org/10.1109/MEMSYS.2009.4805469

2008

  • J. Salvia, M. Messana, M. Ohline, M. Hopcroft, R. Melamud, S. Chandorkar, H. Lee, G. Bahl, B. Murmann, and T. Kenny, “Exploring the limits and practicality of Q-based temperature compensation for silicon resonators,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2008, pp. 1-4. http://dx.doi.org/10.1109/IEDM.2008.4796783
  • A. Dastgheib and B. Murmann, “Calculation of Total Integrated Noise in Analog Circuits,” IEEE Trans. Circuits Syst. I, vol. 55, no. 10, pp. 2988-2993, Nov. 2008. http://dx.doi.org/10.1109/TCSI.2008.923276
  • P. Nikaeen and B. Murmann, “Digital correction of dynamic track-and-hold errors providing SFDR > 83 dB up to fin = 470 MHz,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 161-164. http://dx.doi.org/10.1109/CICC.2008.4672048
  • B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 105-112. http://dx.doi.org/10.1109/CICC.2008.4672032  * * Best Invited Paper Award. * *
  • J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2008, pp. 216-217. http://dx.doi.org/10.1109/VLSIC.2008.4586012  * * Best Student Paper Award. * *
  • M. El-Chammas and B. Murmann, “General analysis on the impact of phase-skew in time-interleaved ADCs,” in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 2008, pp. 17-20. http://dx.doi.org/10.1109/ISCAS.2008.4541343
  • M. Agarwal, S.A. Chandorkar, H. Mehta, R.N. Candler, B. Kim, M.A. Hopcroft, R. Melamud, C.M. Jha, G. Bahl, G. Yama, T.W. Kenny, and B. Murmann, “A study of electrostatic force nonlinearities in resonant microstructures,” Appl. Phys. Lett., vol. 92, no. 10, p. 104106 (3 pages), Mar. 2008. http://dx.doi.org/10.1063/1.2834707
  • J.W. Kim, B. Murmann, and R. Dutton, “Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices,” in Proc. ISQED, San Jose, CA, Mar. 2008, pp. 429-432. http://dx.doi.org/10.1109/ISQED.2008.4479770

2007

  • B. Murmann and B. Boser, “Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs,” IEEE Trans. Instrum. Meas., vol. 56, no. 6, pp. 2504-2514, Dec. 2007. http://dx.doi.org/10.1109/TIM.2007.907950
  • M. Agarwal, H. Mehta, R.N. Candler, S.A. Chandorkar, B. Kim, M.A. Hopcroft, R. Melamud, G. Bahl, G. Yama, T.W. Kenny, and B. Murmann, “Scaling of amplitude-frequency-dependence nonlinearities in electrostatically transduced microresonators,” J. Appl. Phys., vol. 102, no. 7, p. 074903 (7 pages), Oct. 2007. http://dx.doi.org/10.1063/1.2785018
  • Y. Oh and B. Murmann, “A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2007, pp. 193-196. http://dx.doi.org/10.1109/CICC.2007.4405711
  • Shu-Jen Han, Heng Yu, B. Murmann, N. Pourmand, and S. Wang, “A High-Density Magnetoresistive Biosensor Array with Drift-Compensation Mechanism,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2007, pp. 168-594. http://dx.doi.org/10.1109/ISSCC.2007.373347
  • M. Agarwal, K.K. Park, S.A. Chandorkar, R.N. Candler, B. Kim, M.A. Hopcroft, R. Melamud, T.W. Kenny, and B. Murmann, “Acceleration sensitivity in beam-type electrostatic microresonators,” Appl. Phys. Lett., vol. 90, no. 1, p. 014103 (3 pages), Jan. 2007. http://dx.doi.org/10.1063/1.2426884
  • M. Agarwal, H. Mehta, R. Candler, S. Chandorkar, Bongsang Kim, M. Hopcroft, R. Melamud, G. Bahl, G. Yama, T. Kenny, and B. Murmann, “Impact of miniaturization on the current handling of electrostatic MEMS resonators,” in Proc. IEEE MEMS, Kobe, Japan, Jan. 2007, pp. 783-786. http://dx.doi.org/10.1109/MEMSYS.2007.4433092

2006

  • A. Nikoozadeh and B. Murmann, “An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch,” IEEE Trans. Circuits Syst. II, vol. 53, no. 12, pp. 1398-1402, Dec. 2006. http://dx.doi.org/10.1109/TCSII.2006.883204
  • M. Agarwal, S.A. Chandorkar, R.N. Candler, B. Kim, M.A. Hopcroft, R. Melamud, C.M. Jha, T.W. Kenny, and B. Murmann, “Optimal drive condition for nonlinearity reduction in electrostatic microresonators,” Appl. Phys. Lett., vol. 89, no. 21, p. 214105 (3 pages), Nov. 2006. http://dx.doi.org/10.1063/1.2388886
  • B. Murmann, “Digitally Assisted Analog Circuits,” in Proc. IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software, Dallas, Tx, Oct. 2006, pp. 23-30. http://dx.doi.org/10.1109/DCAS.2006.321026
  • J. Chun and B. Murmann, “Analysis and Measurement of Signal Distortion due to ESD Protection Circuits,” IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2354-2358, Oct. 2006. http://dx.doi.org/10.1109/JSSC.2006.881550
  • B. Murmann, P. Nikaeen, D. Connelly, and R. Dutton, “Impact of Scaling on Analog Performance and Associated Modeling Needs,” IEEE Trans. Electron Dev., vol. 53, no. 9, pp. 2160-2167, Sep. 2006. http://dx.doi.org/10.1109/TED.2006.880372
  • B. Sheahan, J. Fattaruso, J. Wong, K. Muth, and B. Murmann, “4.25 Gb/s laser driver: design challenges and EDA tool limitations,” in Proc. Design Automation Conference, San Francisco, CA, Jul. 2006, pp. 863-866. http://dx.doi.org/10.1109/DAC.2006.229243
  • M. Agarwal, K.K. Park, R.N. Candler, B. Kim, M.A. Hopcroft, S.A. Chandorkar, C.M. Jha, R. Melamud, T.W. Kenny, and B. Murmann, “Nonlinear Characterization of Electrostatic MEMS Resonators,” in Proc. IEEE Int. Freq. Control Symp., Miami, FL, Jun. 2006, pp. 209-212. http://dx.doi.org/10.1109/FREQ.2006.275380
  • M.A. Hopcroft, M. Agarwal, K.K. Park, B. Kim, C.M. Jha, R.N. Candler, G. Yama, B. Murmann, and T.W. Kenny, “Temperature Compensation of a MEMS Resonator Using Quality Factor as a Thermometer,” in Proc. IEEE MEMS, Istanbul, Turkey, Jan. 2006, pp. 222-225. http://dx.doi.org/10.1109/MEMSYS.2006.1627776
  • M. Agarwal, K.K. Park, M. Hopcroft, S. Chandorkar, R.N. Candler, B. Kim, R. Melamud, G. Yama, B. Murmann, and T.W. Kenny, “Effects of Mechanical Vibrations and Bias Voltage Noise on Phase Noise of MEMS Resonator Based Oscillators,” in Proc. IEEE MEMS, Istanbul, Turkey, Jan. 2006, pp. 154-157. http://dx.doi.org/10.1109/MEMSYS.2006.1627759

2005

  • M. Agarwal, K. Park, R. Candler, M. Hopcroft, C. Jha, R. Melamud, B. Kim, B. Murmann, and T. Kenny, “Non-linearity cancellation in MEMS resonators for improved power-handling,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2005, pp. 286-289. http://dx.doi.org/10.1109/IEDM.2005.1609330
  • E. Iroaga, L. Nathawad, and B. Murmann, “A background correction technique for timing errors in time-interleaved analog-to-digital converters,” in Proc. IEEE Int. Symp. Circuits Syst., Kobe, Japan, May 2005, vol. 6, pp. 5557-5560. http://dx.doi.org/10.1109/ISCAS.2005.1465896
  • S. Arekapudi, E. Iroaga, and B. Murmann, “A low-power distributed wide-band LNA in 0.18 μm CMOS,” in Proc. IEEE Int. Symp. Circuits Syst., Kobe, Japan, May 2005, vol. 5, pp. 5055-5058. http://dx.doi.org/10.1109/ISCAS.2005.1465770

2004

2003

  • B. Murmann and B. Boser, “A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003. http://dx.doi.org/10.1109/JSSC.2003.819167

Books and Book Chapters

  • B. Murmann and B. Hoefflinger (eds.), “NANO-CHIPS 2030: On-Chip AI for an Efficient Data-Driven World,” Springer, 2020. DOI
  • B. Murmann, M. Verhelst, and Y. Manoli, “Analog-to-Information Conversion,” in NANO-CHIPS 2030, by B. Murmann and B. Hoefflinger (eds.), Springer, 2020. DOI
  • M. Verhelst and B. Murmann, “Machine Learning at the Edge,” in NANO-CHIPS 2030, by B. Murmann and B. Hoefflinger (eds.), Springer, 2020. DOI
  • P.G.A. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits, Cambridge University Press, 2017. DOI
  • B. Murmann, K. Zheng and R. Boesch, “Equalization and A/D Conversion for High-Speed Links,” in Selected Topics in RF, Analog and Mixed Signal Circuits and Systems, by K. Gunnam, M. Vahidfar (eds.), River Publishers, 2017. WWW
  • M. Keller, B. Murmann, and Y. Manoli, “Analog-Digital Interfaces—Review and Current Trends,” in CHIPS 2020 VOL. 2, by B. Hoefflinger (ed.), Springer, 2016. WWW
  • M. Elliott and B. Murmann, “High-Performance Pipelined ADCs for Wireless Infrastructure Systems,” in Advances in Analog and RF IC Design for Wireless Communication Systems, by G. Manganaro and D.M.W. Leenaerts (eds.), Elsevier, 2013. WWW
  • B. Murmann, Analysis and Design of Elementary MOS Amplifier Stages, NTS Press, 2013 WWW
  • M. El-Chammas and B. Murmann, Background Calibration of Time-Interleaved Data Converters, Springer, 2012. WWW
  • M. Keller, B. Murmann, and Y. Manoli, “Analog-Digital Interfaces,” in CHIPS 2020, by B. Hoefflinger (ed.), Springer, 2012. WWW
  • B. Murmann, “Low-Power Pipelined A/D Conversion,” in Analog Circuit Design, by M. Steyaert, A.H.M. Roermund, A. Baschirotto (eds.), Springer, 2011. DOI
  • B. Murmann, “Limits on ADC Power Dissipation,” in Analog Circuit Design, by M. Steyaert, A.H.M. Roermund, J.H. van Huijsing (eds.), Springer, 2006. WWW
  • B. Murmann and B. E. Boser, Digitally Assisted Pipeline ADCs, Kluwer Academic Publishers, 2004. WWW

Patents

  • B. Murmann, D.G. Muratore, E.J. Chichilnisky, P. Tandon, “Data-compressive sensor array,” WO2020082081A1. WWW
  • C. Gupta, R. Walker, B. Murmann, R. Howe, “Mesoscale system feedback-induced dissipation and noise suppression,” US20190137425A1. WWW
  • S. Hori and B. Murmann, “Filtering circuit with jammer generator,” US 8351842, Jan. 8, 2013. WWW
  • B. Murmann and Y. Oh, “Arrangements and methods for providing compensation for non-idealities of components in communications systems,” US 8290031, Oct. 16, 2012. WWW
  • B. Murmann and J. Hu, “Method and system for FET-based amplifier circuits,” US 7791410, Sep. 10, 2010. WWW
  • E. Iroaga and B. Murmann, “Method and system for driver circuits of capacitive loads,” US 7369080, May 6, 2008. WWW

PhD Theses