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publications [2023/10/08 14:44] – [2023] murmannpublications [2023/12/18 10:28] – [2023] murmann
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 +  * M. Jang, M. Hays, W.-H. Yu, C. Lee, P. Caragiulo, A. Ramkaj, P. Wang, A.J. Phillips, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, D.G. Muratore, "A 1024-Channel 268 nW/pixel 36×36 um2/channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," to appear, IEEE J. Solid-State Circuits.
  
   * L.R. Upton, A. Levy, M.D. Scott, D. Rich, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, S. Mitra, P. Raina, and B. Murmann, "EMBER: a 100 MHz, 0.86mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/Bit Read Circuitry," Proc. ESSCIRC, Lisbon, Portugal, Sep. 2023, pp. 469-472. [[https://doi.org/10.1109/ESSCIRC59616.2023.10268807|DOI]]   * L.R. Upton, A. Levy, M.D. Scott, D. Rich, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, S. Mitra, P. Raina, and B. Murmann, "EMBER: a 100 MHz, 0.86mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/Bit Read Circuitry," Proc. ESSCIRC, Lisbon, Portugal, Sep. 2023, pp. 469-472. [[https://doi.org/10.1109/ESSCIRC59616.2023.10268807|DOI]]
  
-  * P. Yan, A. Akhoundi, N.P. Shah, P. Tandon, D.G. Muratore, E.J. Chichilnisky, and Boris Murmann, "Data Compression versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording," IEEE Trans. BioCAS, vol. 17, no. 4, pp. 754-767, Aug. 2023 [[https://doi.org/10.1109/TBCAS.2023.3292058|DOI]]+  * P. Yan, A. Akhoundi, N.P. Shah, P. Tandon, D.G. Muratore, E.J. Chichilnisky, and Boris Murmann, "Data Compression versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording," IEEE Trans. BioCAS, vol. 17, no. 4, pp. 754-767, Aug. 2023. [[https://doi.org/10.1109/TBCAS.2023.3292058|DOI]]
  
   * M. Jang, W.-H. Yu, C. Lee, M. Hays, P. Wang, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, and D.G. Muratore, "A 1024 Channel 268 nW per pixel 36x36 um2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2023, pp. 1-2. [[https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185288|DOI]]   * M. Jang, W.-H. Yu, C. Lee, M. Hays, P. Wang, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, and D.G. Muratore, "A 1024 Channel 268 nW per pixel 36x36 um2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2023, pp. 1-2. [[https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185288|DOI]]

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