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publications [2023/07/22 17:15] – [2023] murmannpublications [2023/12/18 10:28] – [2023] murmann
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 ====== 2023 ====== ====== 2023 ======
  
-  * L.R. Upton, A. Levy1, M.D. Scott, D. Rich, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, S. Mitra, P. Raina, and B. Murmann, "EMBER: a 100 MHz, 0.86mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/Bit Read Circuitry," ESSCIRC 2023.+  * M. Jang, M. Hays, W.-H. Yu, C. Lee, P. Caragiulo, A. Ramkaj, P. Wang, A.J. Phillips, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, D.G. Muratore, "A 1024-Channel 268 nW/pixel 36×36 um2/channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," to appear, IEEE J. Solid-State Circuits.
  
-  * P. Yan, A. Akhoundi, N.P. Shah, P. Tandon, D.G. Muratore, E.J. Chichilnisky, and Boris Murmann, "Data Compression versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording," IEEE Trans. BioCAS, 2023. [[https://doi.org/10.1109/TBCAS.2023.3292058|DOI]]+  * L.R. Upton, A. Levy, M.D. Scott, D. Rich, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, S. Mitra, P. Raina, and B. Murmann, "EMBER: a 100 MHz, 0.86mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/Bit Read Circuitry," Proc. ESSCIRC, Lisbon, Portugal, Sep. 2023, pp. 469-472. [[https://doi.org/10.1109/ESSCIRC59616.2023.10268807|DOI]]
  
-  * M. Jang, W.-H. Yu, C. Lee, M. Hays, P. Wang, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, and D.G. Muratore, "A 1024 Channel 268 nW per pixel 36x36 um2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2023, pp. 1-2.+  * P. Yan, A. Akhoundi, N.P. Shah, P. Tandon, D.G. Muratore, E.J. Chichilnisky, and Boris Murmann, "Data Compression versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording," IEEE Trans. BioCAS, vol. 17, no. 4, pp. 754-767, Aug. 2023. [[https://doi.org/10.1109/TBCAS.2023.3292058|DOI]] 
 + 
 +  * M. Jang, W.-H. Yu, C. Lee, M. Hays, P. Wang, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, and D.G. Muratore, "A 1024 Channel 268 nW per pixel 36x36 um2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2023, pp. 1-2. [[https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185288|DOI]]
  
   * S. Weinreich and B. Murmann, "A 0.6–1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer," IEEE J. Solid-State Circuits, vol. 58, no. 6, pp. 1508-1518, Jun. 2023. [[https://doi.org/10.1109/JSSC.2022.3214226|DOI]]   * S. Weinreich and B. Murmann, "A 0.6–1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer," IEEE J. Solid-State Circuits, vol. 58, no. 6, pp. 1508-1518, Jun. 2023. [[https://doi.org/10.1109/JSSC.2022.3214226|DOI]]
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   * D.M. Stipanović, M.N. Kapetina, M.R. Rapaić, and B. Murmann, "Stability of Gated Recurrent Unit Neural Networks: Convex Combination Formulation Approach," J. Optim. Theory Appl., Nov. 2020. [[http://doi.org/10.1007/s10957-020-01776-w|DOI]]   * D.M. Stipanović, M.N. Kapetina, M.R. Rapaić, and B. Murmann, "Stability of Gated Recurrent Unit Neural Networks: Convex Combination Formulation Approach," J. Optim. Theory Appl., Nov. 2020. [[http://doi.org/10.1007/s10957-020-01776-w|DOI]]
          
-  * Wei-Hsiang Ho, Yi-Hsun Hsieh, B. Murmann, and Wei-Zen Chen, "A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4' [[http://dx.doi.org/10.1109/ISCAS45731.2020.9180483|DOI]]+  * Wei-Hsiang Ho, Yi-Hsun Hsieh, B. Murmann, and Wei-Zen Chen, "A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4. [[http://dx.doi.org/10.1109/ISCAS45731.2020.9180483|DOI]]
  
   * S. Weinreich, D. Muratore, Y. Chae, T. McKay, and B. Murmann, "Implications of Finite Clock Transition Time for LPTV Circuit Analysis," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4. [[http://dx.doi.org/10.1109/ISCAS45731.2020.9180691|DOI]]   * S. Weinreich, D. Muratore, Y. Chae, T. McKay, and B. Murmann, "Implications of Finite Clock Transition Time for LPTV Circuit Analysis," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4. [[http://dx.doi.org/10.1109/ISCAS45731.2020.9180691|DOI]]
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   * E. Iroaga and B. Murmann, "Method and system for driver circuits of capacitive loads," US 7369080, May 6, 2008. [[https://patents.google.com/patent/US7369080B1|WWW]]   * E. Iroaga and B. Murmann, "Method and system for driver circuits of capacitive loads," US 7369080, May 6, 2008. [[https://patents.google.com/patent/US7369080B1|WWW]]
 ====== PhD Theses  ====== ====== PhD Theses  ======
 +  * G. Nyikayaramba, "Enabling low voltage electronics for ultrasonic structural health monitoring," 2023 [[https://searchworks.stanford.edu/view/in00000001244]]
 +  
   * Q. Lu, "TinyML computer vision using coarsely-quantized log-gradient input images," 2023 [[https://searchworks.stanford.edu/view/14801748]]   * Q. Lu, "TinyML computer vision using coarsely-quantized log-gradient input images," 2023 [[https://searchworks.stanford.edu/view/14801748]]
  

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