Ilina_Mitra
<br>
BSEE, Princeton University, 2012<br> Research: Automated Layout Generation of Circuit Schematics Email: ilinam AT stanford DOT edu <br> <br> <br> As transistors become smaller and circuit designs become more complex, parasitics play an increasing role in circuit design. Circuit designers find that parastic behavior due to the physical layout of their designs has a large enough impact on performance that they must adjust their designs accordingly. The latency between schematic design and layout generation prevents designers from rapidly iterating their designs, and has become a bottleneck in industry. This project aims to automate the layout generation process in real time so that circuit designers may see the effects of parasitics as they are designing their schematics. Such a technology would be an effective way to allow designers to adjust their designs on an ongoing basis, thus reducing this current bottleneck.
