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| po-hsuan_wei [2020/11/04 12:37] – [Layout Generation Flow] pohsuan | po-hsuan_wei [2020/11/04 12:53] (current) – [Layout Generation Flow] pohsuan |
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| ====== Po-Hsuan Wei ====== | ====== Po-Hsuan Wei ====== |
| | ~~NOTOC~~ |
| {{wiki:Headshot_PHW.jpg?320x214|Headshot_PHW.jpg}} | {{wiki:Headshot_PHW.jpg?320x214|Headshot_PHW.jpg}} |
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| ====== Automated Layout Generation for Analog Circuits ====== | ====== Automated Layout Generation for Analog Circuits ====== |
| ==== Layout is the Bottleneck of Analog and Mixed-Signal (AMS) Designs ==== | ==== Layout is the Bottleneck of Analog and Mixed-Signal (AMS) Designs ==== |
| System-on-chips today are more than 80% digital [[1]]. As digital components are the major part of the system, FinFET, with low leakage power and high operation speed, is highly favorable. While exhibiting the desired characteristics, the layout for FinFET has become more complex than ever. For one, the shrunken feature size mandates the use of more design rules, both in quantity and complexity. The back-end-of-line is fabricated with multiple patterning, which translates to a metal coloring problem. Moreover, the routing is based on a grid-like layout with either horizontal or vertical direction for different metal layers, thus reducing the number of feasible solutions to circuit routing. Secondly, FinFET has severe layout-dependent effects, whose aggregated impact can only be observed from post-layout simulation. To increase the intrinsic gain, high stress is applied to the front-end-of-line, and thus the placement of the circuit components can greatly impact the characteristics of the devices. [[2]] The reduced wire width leads to higher resistance, causing voltage biases to degrade at an already low supply voltage. The inclusion of the middle-of-line layer and the 3D structure of FinFET inevitably increases the parasitic capacitance. The sheer number of design rules combined with significant layout-dependent effects results in several schematic-layout-simulation iterations, prolonging the turnaround time. In the case of AMS designs, where the layout is mostly done manually, such an iteration takes even longer to complete, and the designers have little power over the layout of their circuits. | System-on-chips today are more than 80% digital [1]. As digital components are the major part of the system, FinFET, with low leakage power and high operation speed, is highly favorable. While exhibiting the desired characteristics, the layout for FinFET has become more complex than ever. For one, the shrunken feature size mandates the use of more design rules, both in quantity and complexity. The back-end-of-line is fabricated with multiple patterning, which translates to a metal coloring problem. Moreover, the routing is based on a grid-like layout with either horizontal or vertical direction for different metal layers, thus reducing the number of feasible solutions to circuit routing. Secondly, FinFET has severe layout-dependent effects, whose aggregated impact can only be observed from post-layout simulation. To increase the intrinsic gain, high stress is applied to the front-end-of-line, and thus the placement of the circuit components can greatly impact the characteristics of the devices. [2] The reduced wire width leads to higher resistance, causing voltage biases to degrade at an already low supply voltage. The inclusion of the middle-of-line layer and the 3D structure of FinFET inevitably increases the parasitic capacitance. The sheer number of design rules combined with significant layout-dependent effects results in several schematic-layout-simulation iterations, prolonging the turnaround time. In the case of AMS designs, where the layout is mostly done manually, such an iteration takes even longer to complete, and the designers have little power over the layout of their circuits. |
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| ==== Automation Comes to the Rescue for AMS Designers ==== | ==== Automation Comes to the Rescue for AMS Designers ==== |
| Our approach aims to shorten and automate the iteration loop, preserve analog design intent systematically, leverage CPU power and free the engineers from having to labor over design rules. Moreover, our tool opens up the possibility of system-level layout optimization by producing multiple layouts with various performance profiles, all from the same schematic design. We have recently taped out a prototype IC using the proposed layout generation flow. | Our approach aims to shorten and automate the iteration loop, preserve analog design intent systematically, leverage CPU power and free the engineers from having to labor over design rules. Moreover, our tool opens up the possibility of system-level layout optimization by producing multiple layouts with various performance profiles, all from the same schematic design. We have recently taped out a prototype IC using the proposed layout generation flow. |
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| {{wiki:Research Profile Figures PHW 20170720.png?800x374|Research Profile Figures PHW 20170720.png}} | {{wiki:Research Profile Figures PHW 20170720.png?800x374}} |
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| Figure 1. Explosion of Design Rules [[3]];Figure 2. Proposed Automated Layout Generation Flow for AMS Circuits | Figure 1. Explosion of Design Rules [3] Figure 2. Proposed Automated Layout Generation Flow for AMS Circuits |
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| [[1]] P. Kinget, "Designing analog and RF circuits in nanoscale CMOS technologies: Scale the supply, reduce the area and use digital gates", Proc. IEEE Int. Conf. Microwaves, Communications, Antennas and Electronics Systems, pp. 1, 2009 \\ | \\ |
| [[2]] K. -W. Su, Y. -M. Sheu, C. -K. Lin, S. -J. Yang, W. -J. Liang, X. Xi, C. -S. Chiang, J. -K. Her, Y. -T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” 2003, pp. 245–248. \\ | [1] P. Kinget, "Designing analog and RF circuits in nanoscale CMOS technologies: Scale the supply, reduce the area and use digital gates", Proc. IEEE Int. Conf. Microwaves, Communications, Antennas and Electronics Systems, pp. 1, 2009 \\ |
| [[3]] http://www.electronicdesign.com/eda/are-you-really-ready-your-next-node | [2] K. -W. Su, Y. -M. Sheu, C. -K. Lin, S. -J. Yang, W. -J. Liang, X. Xi, C. -S. Chiang, J. -K. Her, Y. -T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” 2003, pp. 245–248. \\ |
| | [3] http://www.electronicdesign.com/eda/are-you-really-ready-your-next-node |
