Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
athanasios_thanos_ramkaj [2021/10/03 20:00] – aramkaj | athanasios_thanos_ramkaj [2021/10/03 20:07] (current) – aramkaj | ||
---|---|---|---|
Line 3: | Line 3: | ||
{{athanasiosramkaj.jpg? | {{athanasiosramkaj.jpg? | ||
- | * **Ph.D. (//summa cum laude//) in Electrical Engineering** :: KU Leuven, Leuven, Belgium (2021) | + | * **Ph.D. (//summa cum laude//) in Electrical Engineering** **::** KU Leuven, Leuven, Belgium (2021) |
- | * **M.Sc. (//cum laude//) in Electrical Engineering** :: TU Delft, Delft, the Netherlands (2014) | + | * **M.Sc. (//cum laude//) in Electrical Engineering** **::** TU Delft, Delft, the Netherlands (2014) |
- | * **B.Sc. in Physics** :: Aristotle University, Thessaloniki, | + | * **B.Sc. in Physics** **::** Aristotle University, Thessaloniki, |
**Email**: aramkaj(AT)stanford(DOT)edu | **Email**: aramkaj(AT)stanford(DOT)edu | ||
Line 12: | Line 12: | ||
====== Multi-GHz Ultra-Low Jitter High-Linearity Data Converter Systems ====== | ====== Multi-GHz Ultra-Low Jitter High-Linearity Data Converter Systems ====== | ||
- | Investigating architecture and circuit solutions in both advanced CMOS and BiCMOS technologies to realize next-generation RF data converter systems with multiple tens of gigahertz bandwidth (> 20GHz), ultra-low jitter (< 40fs), and high-linearity (> 65dB). | + | Investigating architecture and circuit solutions in advanced CMOS and BiCMOS technologies to realize next-generation RF data converter systems with multiple tens of gigahertz bandwidth (> 20GHz), ultra-low jitter (< 40fs including clock generation), and high-linearity (> 65dB SFDR, |IMD< |