Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision
Previous revision
publications [2022/06/28 18:04] – [PhD Theses] murmannpublications [2023/12/31 10:15] (current) – [2023] murmann
Line 4: Line 4:
  
 **[[https://orcid.org/0000-0003-3417-8782|ORCID Profile]]** **[[https://orcid.org/0000-0003-3417-8782|ORCID Profile]]**
 +
 +====== 2023 ======
 +
 +  * M. Jang, M. Hays, W.-H. Yu, C. Lee, P. Caragiulo, A. Ramkaj, P. Wang, A.J. Phillips, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, D.G. Muratore, "A 1024-Channel 268 nW/pixel 36×36 um2/channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," IEEE J. Solid-State Circuits. [[https://doi.org/10.1109/JSSC.2023.3344798|DOI]]
 +
 +  * L.R. Upton, A. Levy, M.D. Scott, D. Rich, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, S. Mitra, P. Raina, and B. Murmann, "EMBER: a 100 MHz, 0.86mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/Bit Read Circuitry," Proc. ESSCIRC, Lisbon, Portugal, Sep. 2023, pp. 469-472. [[https://doi.org/10.1109/ESSCIRC59616.2023.10268807|DOI]]
 +
 +  * P. Yan, A. Akhoundi, N.P. Shah, P. Tandon, D.G. Muratore, E.J. Chichilnisky, and Boris Murmann, "Data Compression versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording," IEEE Trans. BioCAS, vol. 17, no. 4, pp. 754-767, Aug. 2023. [[https://doi.org/10.1109/TBCAS.2023.3292058|DOI]]
 +
 +  * M. Jang, W.-H. Yu, C. Lee, M. Hays, P. Wang, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, and D.G. Muratore, "A 1024 Channel 268 nW per pixel 36x36 um2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2023, pp. 1-2. [[https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185288|DOI]]
 +
 +  * S. Weinreich and B. Murmann, "A 0.6–1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer," IEEE J. Solid-State Circuits, vol. 58, no. 6, pp. 1508-1518, Jun. 2023. [[https://doi.org/10.1109/JSSC.2022.3214226|DOI]]
 +
 +  * A. Ramkaj, M. Perrott, B. Haroun, and B. Murmann, "High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, May 2023, pp. 1-5. [[https://doi.org/10.1109/ISCAS46773.2023.10181490|DOI]]
 +
 +  * Q. Lu and B. Murmann, "Enhancing the Energy Efficiency and Robustness of tinyML Computer Vision Using Log-Gradient Images," ACM Trans. Embedded Computing Systems. [[https://doi.org/10.1145/3591466|DOI]]
 +
 +  * R.P. Martinez, D.J. Munzer, B. Shankar, B. Murmann, and S. Chowdhury, "Linearity Performance of Derivative Superposition in GaN HEMTs: A Device-to-Circuit Perspective," IEEE Trans. Electron Devices., vol. 70, no. 5, pp. 2247-2254, May 2023. [[https://doi.org/10.1109/TED.2023.3259383|DOI]]
 +
 +  *  K. Mohamed, K.Y. Yasseen, B. Murmann and H. Omran, "Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables," IEEE Access, vol. 11, pp. 41205-41217, Apr. 2023. [[https://doi.org/10.1109/ACCESS.2023.3270106|DOI]].
 +
 +  * L.R. Upton, G. Lallement, M.D. Scott, J. Taylor, R.M. Radway, D. Rich, M. Nelson, S. Mitra, and B. Murmann, "Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices," Proc. ISQED, Apr. 2023, pp 1-7. [[https://doi.org/10.1109/ISQED57927.2023.10129298|DOI]]
 + 
 +  * U. Kraft, M. Nikolka, G.‐J. N. Wang, Y. Kim, R. Pfattner, M. Alsufyani, I. McCulloch, B. Murmann, and Z. Bao, "Low-voltage polymer transistors on hydrophobic dielectrics and surfaces," J. Phys. Mater., vol. 6, no. 2, Mar. 2023. [[https://doi.org/10.1088/2515-7639/acb7a1|DOI]]
 + 
 +  * V. Kesler, K. Fu, Y. Chen, C.H. Park, M. Eisenstein, B. Murmann, and H.T. Soh, "Tailoring Electrode Surface Charge to Achieve Discrimination and Quantification of Chemically Similar Small Molecules with Electrochemical Aptamers," Adv. Funct. Mater., 33:2370001, Jan. 2023. [[https://doi.org/10.1002/adfm.202370001|DOI]]
 +
 ====== 2022 ====== ====== 2022 ======
-  * P. Caragiulo, A. Ramkaj, A. Arbabian, and B. Murmann, "A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16 nm FinFET CMOS," to appear, IEEE European Solid-State Circuits Conference, Sep. 2022.+ 
 +  * M.L. Wang, A. Singhvi, G. Nyikayaramba, B. Murmann, and A. Arbabian, "Adaptive Beamforming for Wireless Powering of a Network of Ultrasonic Implants," IEEE International Ultrasonics Symposium, Venice, Italy, Oct. 2022. 
 + 
 +  * P. Yan, N.P. Shah, D.G. Muratore, P. Tandon, E.J. Chichilnisky, and B. Murmann, "Data Compression versus Signal Fidelity Tradeoff in Wired-OR ADC Arrays for Neural Recording," IEEE Biomedical Circuits and Systems Conference (BioCAS), Taipei, Taiwan, Oct. 2022, pp. 80-84. [[http://doi.org/10.1109/BioCAS54905.2022.9948677|DOI]] 
 + 
 +  * B. Murmann, "Mixed-Signal Circuit Design for the Data-Driven World," Proc. International Conference on Solid State Devices and Materials, Makuhari, Japan, Sep. 2022, pp. 770-771. [[http://www.ssdm.jp/|URL]] 
 + 
 +  * P. Caragiulo, A. Ramkaj, A. Arbabian, and B. Murmann, "A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16 nm FinFET CMOS," Proc. IEEE European Solid-State Circuits Conference, Milan, Italy, Sep. 2022, pp. 329-332. [[http://doi.org/10.1109/ESSCIRC55480.2022.9911426|DOI]] 
 + 
 +  * S. Weinreich and B. Murmann, "A Single-Transistor Amplifier with Back-Gate Feedback in 22-nm FD-SOI," IEEE Solid-State Circuits Letters, vol. 5, pp. 210-213, 2022. [[http://doi.org/10.1109/LSSC.2022.3198547|DOI]]
  
   * K. Prabhu, A. Gural, Z.F. Khan, R.M. Radway, M. Giordano, K. Koul, R. Doshi, J.W. Kustin, T. Liu, G.B. Lopes, V. Turbiner, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, G. Lallement, B. Murmann, S. Mitra, and P. Raina, "CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference," IEEE J. Solid-State Circuits, vol. 57, no. 4, pp. 1013-1026, Apr. 2022. [[http://doi.org/10.1109/JSSC.2022.3140753|DOI]]   * K. Prabhu, A. Gural, Z.F. Khan, R.M. Radway, M. Giordano, K. Koul, R. Doshi, J.W. Kustin, T. Liu, G.B. Lopes, V. Turbiner, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, G. Lallement, B. Murmann, S. Mitra, and P. Raina, "CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference," IEEE J. Solid-State Circuits, vol. 57, no. 4, pp. 1013-1026, Apr. 2022. [[http://doi.org/10.1109/JSSC.2022.3140753|DOI]]
Line 52: Line 88:
   * D.M. Stipanović, M.N. Kapetina, M.R. Rapaić, and B. Murmann, "Stability of Gated Recurrent Unit Neural Networks: Convex Combination Formulation Approach," J. Optim. Theory Appl., Nov. 2020. [[http://doi.org/10.1007/s10957-020-01776-w|DOI]]   * D.M. Stipanović, M.N. Kapetina, M.R. Rapaić, and B. Murmann, "Stability of Gated Recurrent Unit Neural Networks: Convex Combination Formulation Approach," J. Optim. Theory Appl., Nov. 2020. [[http://doi.org/10.1007/s10957-020-01776-w|DOI]]
          
-  * Wei-Hsiang Ho, Yi-Hsun Hsieh, B. Murmann, and Wei-Zen Chen, "A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4[[http://dx.doi.org/10.1109/ISCAS45731.2020.9180483|DOI]]+  * Wei-Hsiang Ho, Yi-Hsun Hsieh, B. Murmann, and Wei-Zen Chen, "A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4[[http://dx.doi.org/10.1109/ISCAS45731.2020.9180483|DOI]]
  
   * S. Weinreich, D. Muratore, Y. Chae, T. McKay, and B. Murmann, "Implications of Finite Clock Transition Time for LPTV Circuit Analysis," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4. [[http://dx.doi.org/10.1109/ISCAS45731.2020.9180691|DOI]]   * S. Weinreich, D. Muratore, Y. Chae, T. McKay, and B. Murmann, "Implications of Finite Clock Transition Time for LPTV Circuit Analysis," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4. [[http://dx.doi.org/10.1109/ISCAS45731.2020.9180691|DOI]]
Line 489: Line 525:
   * E. Iroaga and B. Murmann, "Method and system for driver circuits of capacitive loads," US 7369080, May 6, 2008. [[https://patents.google.com/patent/US7369080B1|WWW]]   * E. Iroaga and B. Murmann, "Method and system for driver circuits of capacitive loads," US 7369080, May 6, 2008. [[https://patents.google.com/patent/US7369080B1|WWW]]
 ====== PhD Theses  ====== ====== PhD Theses  ======
 +  * G. Nyikayaramba, "Enabling low voltage electronics for ultrasonic structural health monitoring," 2023 [[https://searchworks.stanford.edu/view/in00000001244]]
 +  
 +  * Q. Lu, "TinyML computer vision using coarsely-quantized log-gradient input images," 2023 [[https://searchworks.stanford.edu/view/14801748]]
 +
 +  * S. Weinreich, "Linear periodically time-varying circuits for the Internet of Everything," 2022 [[https://searchworks.stanford.edu/view/14310526]]
  
   * V. Kesler, "Bioelectronic interfaces for molecular quantification," 2022 [[https://searchworks.stanford.edu/view/14233969]]   * V. Kesler, "Bioelectronic interfaces for molecular quantification," 2022 [[https://searchworks.stanford.edu/view/14233969]]