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publications [2021/06/06 12:20] – [2021] murmannpublications [2023/12/31 10:15] (current) – [2023] murmann
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 **[[https://orcid.org/0000-0003-3417-8782|ORCID Profile]]** **[[https://orcid.org/0000-0003-3417-8782|ORCID Profile]]**
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 +====== 2023 ======
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 +  * M. Jang, M. Hays, W.-H. Yu, C. Lee, P. Caragiulo, A. Ramkaj, P. Wang, A.J. Phillips, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, D.G. Muratore, "A 1024-Channel 268 nW/pixel 36×36 um2/channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," IEEE J. Solid-State Circuits. [[https://doi.org/10.1109/JSSC.2023.3344798|DOI]]
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 +  * L.R. Upton, A. Levy, M.D. Scott, D. Rich, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, S. Mitra, P. Raina, and B. Murmann, "EMBER: a 100 MHz, 0.86mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/Bit Read Circuitry," Proc. ESSCIRC, Lisbon, Portugal, Sep. 2023, pp. 469-472. [[https://doi.org/10.1109/ESSCIRC59616.2023.10268807|DOI]]
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 +  * P. Yan, A. Akhoundi, N.P. Shah, P. Tandon, D.G. Muratore, E.J. Chichilnisky, and Boris Murmann, "Data Compression versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording," IEEE Trans. BioCAS, vol. 17, no. 4, pp. 754-767, Aug. 2023. [[https://doi.org/10.1109/TBCAS.2023.3292058|DOI]]
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 +  * M. Jang, W.-H. Yu, C. Lee, M. Hays, P. Wang, N. Vitale, P. Tandon, P. Yan, P.-I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, and D.G. Muratore, "A 1024 Channel 268 nW per pixel 36x36 um2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2023, pp. 1-2. [[https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185288|DOI]]
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 +  * S. Weinreich and B. Murmann, "A 0.6–1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer," IEEE J. Solid-State Circuits, vol. 58, no. 6, pp. 1508-1518, Jun. 2023. [[https://doi.org/10.1109/JSSC.2022.3214226|DOI]]
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 +  * A. Ramkaj, M. Perrott, B. Haroun, and B. Murmann, "High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, May 2023, pp. 1-5. [[https://doi.org/10.1109/ISCAS46773.2023.10181490|DOI]]
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 +  * Q. Lu and B. Murmann, "Enhancing the Energy Efficiency and Robustness of tinyML Computer Vision Using Log-Gradient Images," ACM Trans. Embedded Computing Systems. [[https://doi.org/10.1145/3591466|DOI]]
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 +  * R.P. Martinez, D.J. Munzer, B. Shankar, B. Murmann, and S. Chowdhury, "Linearity Performance of Derivative Superposition in GaN HEMTs: A Device-to-Circuit Perspective," IEEE Trans. Electron Devices., vol. 70, no. 5, pp. 2247-2254, May 2023. [[https://doi.org/10.1109/TED.2023.3259383|DOI]]
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 +  *  K. Mohamed, K.Y. Yasseen, B. Murmann and H. Omran, "Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables," IEEE Access, vol. 11, pp. 41205-41217, Apr. 2023. [[https://doi.org/10.1109/ACCESS.2023.3270106|DOI]].
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 +  * L.R. Upton, G. Lallement, M.D. Scott, J. Taylor, R.M. Radway, D. Rich, M. Nelson, S. Mitra, and B. Murmann, "Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices," Proc. ISQED, Apr. 2023, pp 1-7. [[https://doi.org/10.1109/ISQED57927.2023.10129298|DOI]]
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 +  * U. Kraft, M. Nikolka, G.‐J. N. Wang, Y. Kim, R. Pfattner, M. Alsufyani, I. McCulloch, B. Murmann, and Z. Bao, "Low-voltage polymer transistors on hydrophobic dielectrics and surfaces," J. Phys. Mater., vol. 6, no. 2, Mar. 2023. [[https://doi.org/10.1088/2515-7639/acb7a1|DOI]]
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 +  * V. Kesler, K. Fu, Y. Chen, C.H. Park, M. Eisenstein, B. Murmann, and H.T. Soh, "Tailoring Electrode Surface Charge to Achieve Discrimination and Quantification of Chemically Similar Small Molecules with Electrochemical Aptamers," Adv. Funct. Mater., 33:2370001, Jan. 2023. [[https://doi.org/10.1002/adfm.202370001|DOI]]
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 +====== 2022 ======
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 +  * M.L. Wang, A. Singhvi, G. Nyikayaramba, B. Murmann, and A. Arbabian, "Adaptive Beamforming for Wireless Powering of a Network of Ultrasonic Implants," IEEE International Ultrasonics Symposium, Venice, Italy, Oct. 2022.
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 +  * P. Yan, N.P. Shah, D.G. Muratore, P. Tandon, E.J. Chichilnisky, and B. Murmann, "Data Compression versus Signal Fidelity Tradeoff in Wired-OR ADC Arrays for Neural Recording," IEEE Biomedical Circuits and Systems Conference (BioCAS), Taipei, Taiwan, Oct. 2022, pp. 80-84. [[http://doi.org/10.1109/BioCAS54905.2022.9948677|DOI]]
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 +  * B. Murmann, "Mixed-Signal Circuit Design for the Data-Driven World," Proc. International Conference on Solid State Devices and Materials, Makuhari, Japan, Sep. 2022, pp. 770-771. [[http://www.ssdm.jp/|URL]]
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 +  * P. Caragiulo, A. Ramkaj, A. Arbabian, and B. Murmann, "A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16 nm FinFET CMOS," Proc. IEEE European Solid-State Circuits Conference, Milan, Italy, Sep. 2022, pp. 329-332. [[http://doi.org/10.1109/ESSCIRC55480.2022.9911426|DOI]]
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 +  * S. Weinreich and B. Murmann, "A Single-Transistor Amplifier with Back-Gate Feedback in 22-nm FD-SOI," IEEE Solid-State Circuits Letters, vol. 5, pp. 210-213, 2022. [[http://doi.org/10.1109/LSSC.2022.3198547|DOI]]
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 +  * K. Prabhu, A. Gural, Z.F. Khan, R.M. Radway, M. Giordano, K. Koul, R. Doshi, J.W. Kustin, T. Liu, G.B. Lopes, V. Turbiner, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, G. Lallement, B. Murmann, S. Mitra, and P. Raina, "CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference," IEEE J. Solid-State Circuits, vol. 57, no. 4, pp. 1013-1026, Apr. 2022. [[http://doi.org/10.1109/JSSC.2022.3140753|DOI]]
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 +  * R. Gottscho, E. Levine, T.-J. K. Liu, P. McIntyre, S. Mitra, B. Murmann, J. Rabaey, S. Salahuddin, W. Shih, and H.-S. P. Wong, "Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies," arXiv:2204.02216 [cs.OH], Mar. 2022. [[https://arxiv.org/abs/2204.02216|URL]]
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 +  * Q. Lu and B. Murmann, "Improving the Energy Efficiency and Robustness of tinyML Computer Vision using Log-Gradient Input Images," Proc. tinyML Research Symposium, Mar. 2022. [[https://arxiv.org/abs/2203.02571|URL]]
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 ====== 2021 ====== ====== 2021 ======
-  * W.-H. Yu, M. GiordanoRDoshiMZhang, P.-I. Mak, R.P. Martins, and B. Murmann, "A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory," to appear at MWSCAS 2021.+  * M. ShafiqueTTheocharidesVJReddy and B. Murmann, "TinyML: Current Progress, Research Challenges, and Future Roadmap," Design Automation Conference (DAC), Dec. 2021, pp. 1303-1306. [[http://doi.org/10.1109/DAC18074.2021.9586232|DOI]]
  
-  * M. Giordano, K. Prabhu, K. Koul, R.MRadwayAGural, RDoshiZ.FKhanJ.W. Kustin, T. Liu, G.B. LopesVTurbiner, Win-San KhwaYu-Der Chih, Meng-Fan Chang, GLallement, B. Murmann, S. Mitra1, and P. Raina"CHIMERA: A 0.92 TOPS2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference," in SympVLSI Circuits Dig., Kyoto, Japan, Jun. 2021.  +  * R.PMartinezD.JMunzerX.YZhou, B. ShankarE.-M. SchmidtKWildnauer, B. Murmann, and S. Chowdhury"Best Practices to Quantify Linearity Performance of GaN HEMTs for Power Amplifier Applications," IEEE Workshop on Wide Bandgap Power Devices and Applications (WiPDA)Nov2021pp85-89[[http://doi.org/10.1109/WiPDA49284.2021.9645120|DOI]]
  
-  * DKanemoto, JSpaulding, and B. Murmann, B. "Single-chip mixer-based subarray beamformer for sub-Nyquist sampling in ultrasound imaging," Japanese Journal of Applied Physics, vol. 60, no. SBpSBBL08Apr. 2021. [[http://doi.org/10.35848/1347-4065/abec8b|DOI]]+  * P.-HWei and B. Murmann, "Analog and Mixed-Signal Layout Automation using Digital Place-and-Route Tools," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 29, no. 11pp1838-1849Nov. 2021. [[http://doi.org/10.1109/TVLSI.2021.3105028|DOI]]
  
-  * YKhanM.LMaurielloPNowruzi, A. Motani, G. Hon, N. VitaleJLi, J. Kim, A. Foudeh, D. Duvio, E. Shols, M. Chesnut, J. Landay, J. Liphardt, L. Williams, K.D. Sudheimer, B. Murmann, Z. Bao, and P.EParedes, "Design considerations of a wearable electronic-skin for mental health and wellness: balancing biosignals and human factors," bioRxiv 2021.01.20.4274962021[[http://doi.org/10.1101/2021.01.20.427496|DOI]]  +  * KFuJ.-WSeoVKesler, N. MaganziniB.D. Wilson, M. Eisenstein, B. Murmann, and H.TSoh, "Accelerated Electron Transfer in Nanostructured Electrodes Improves the Sensitivity of Electrochemical Biosensors," Advanced ScienceOct. 2021. [[http://doi.org/10.1002/advs.202102495|DOI]]
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-  * G.W. Burr, S. Lim, B. Murmann, R. Venkatesan, and M. Verhelst, "Fair and comprehensive benchmarking of machine learning processing chips," IEEE Design & Test. [[http://dx.doi.org/10.1109/MDAT.2021.3063366|DOI]]+
  
-  * P. Caragiulo, O.E. Mattia, A. Arbabian and B. Murmann, "A 2x Time-Interleaved 28-GS/s 8-Bit 0.03-mm² Switched-Capacitor DAC in 16-nm FinFET CMOS," IEEE Journal of Solid-State Circuits, 2021. [[http://dx.doi.org/10.1109/JSSC.2021.3057608|DOI]]+  * W.-H. Yu, M. Giordano, R. Doshi, M. Zhang, P.-I. Mak, R.P. Martins, and B. Murmann, "A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2021. [[http://doi.org/10.1109/MWSCAS47672.2021.9531769|DOI]] 
 + 
 +  * P. Caragiulo, O.E. Mattia, A. Arbabian and B. Murmann, "A 2x Time-Interleaved 28-GS/s 8-Bit 0.03-mm² Switched-Capacitor DAC in 16-nm FinFET CMOS," IEEE J. Solid-State Circuits, vol. 56, no. 8, pp. 2335-2346, Aug. 2021. [[http://dx.doi.org/10.1109/JSSC.2021.3057608|DOI]] 
 + 
 +  * M. Giordano, K. Prabhu, K. Koul, R.M. Radway, A. Gural, R. Doshi, Z.F. Khan, J.W. Kustin, T. Liu, G.B. Lopes, V. Turbiner, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, G. Lallement, B. Murmann, S. Mitra, and P. Raina, "CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference," in Symp. VLSI Circuits Dig., Kyoto, Japan, Jun. 2021, pp. 1-2. [[http://doi.org/10.23919/VLSICircuits52068.2021.9492347|DOI]] **Best Student Paper Award**  
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 +  * D. Kanemoto, J. Spaulding, and B. Murmann, B. "Single-chip mixer-based subarray beamformer for sub-Nyquist sampling in ultrasound imaging," Japanese Journal of Applied Physics, vol. 60, no. SB, p. SBBL08, Apr. 2021. [[http://doi.org/10.35848/1347-4065/abec8b|DOI]]
      
-  * D.A. Villamizar, D.G. Muratore, J.B. Wieser and B. Murmann, "An 800 nW Switched-Capacitor Feature Extraction Filterbank for Sound Classification," IEEE Trans. Circuits and Systems I, vol. 68, no. 4, pp. 1578-1588, April 2021. [[http://dx.doi.org/10.1109/TCSI.2020.3047035|DOI]]+  * D.A. Villamizar, D.G. Muratore, J.B. Wieser and B. Murmann, "An 800 nW Switched-Capacitor Feature Extraction Filterbank for Sound Classification," IEEE Trans. Circuits and Systems I, vol. 68, no. 4, pp. 1578-1588, Apr. 2021. [[http://dx.doi.org/10.1109/TCSI.2020.3047035|DOI]] 
 + 
 +  * G.W. Burr, S. Lim, B. Murmann, R. Venkatesan, and M. Verhelst, "Fair and comprehensive benchmarking of machine learning processing chips," IEEE Design & Test, Mar. 2021. [[http://dx.doi.org/10.1109/MDAT.2021.3063366|DOI]]
  
   * P. Caragiulo, O.E. Mattia, and B. Murmann, “A 112 GS/s Switched-Capacitor DAC in 16 nm FinFET CMOS,” GOMACTech Conference, Mar. 2021.    * P. Caragiulo, O.E. Mattia, and B. Murmann, “A 112 GS/s Switched-Capacitor DAC in 16 nm FinFET CMOS,” GOMACTech Conference, Mar. 2021. 
  
   * W. Jiang, Y. Zhu, C.-H. Chan, B. Murmann and R.P. Martins, "A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler," IEEE Trans. Circuits and Systems I, vol. 68, no. 2, pp. 557-568, Feb. 2021. [[http://dx.doi.org/10.1109/TCSI.2020.3039252|DOI]]    * W. Jiang, Y. Zhu, C.-H. Chan, B. Murmann and R.P. Martins, "A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler," IEEE Trans. Circuits and Systems I, vol. 68, no. 2, pp. 557-568, Feb. 2021. [[http://dx.doi.org/10.1109/TCSI.2020.3039252|DOI]] 
 +
 +  * Y. Khan, M.L. Mauriello, P. Nowruzi, A. Motani, G. Hon, N. Vitale, J. Li, J. Kim, A. Foudeh, D. Duvio, E. Shols, M. Chesnut, J. Landay, J. Liphardt, L. Williams, K.D. Sudheimer, B. Murmann, Z. Bao, and P.E. Paredes, "Design considerations of a wearable electronic-skin for mental health and wellness: balancing biosignals and human factors," bioRxiv 2021.01.20.427496, Jan. 2021. [[http://doi.org/10.1101/2021.01.20.427496|DOI]] 
  
     * W.-H. Ho, Y.-H. Hsieh, B. Murmann and W.-Z. Chen, "A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology," IEEE Open Journal of Circuits and Systems, vol. 2, pp. 56-64, Jan. 2021. [[http://dx.doi.org/10.1109/OJCAS.2020.3036531|DOI]]     * W.-H. Ho, Y.-H. Hsieh, B. Murmann and W.-Z. Chen, "A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology," IEEE Open Journal of Circuits and Systems, vol. 2, pp. 56-64, Jan. 2021. [[http://dx.doi.org/10.1109/OJCAS.2020.3036531|DOI]]
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 ====== 2020 ====== ====== 2020 ======
   * V. Kesler, B. Murmann, and H.T. Soh, "Going Beyond the Debye Length: Overcoming Charge Screening Limitations in Next-Generation Bioelectronic Sensors," ACS Nano, Nov. 2020. [[http://doi.org/10.1021/acsnano.0c08622|DOI]]   * V. Kesler, B. Murmann, and H.T. Soh, "Going Beyond the Debye Length: Overcoming Charge Screening Limitations in Next-Generation Bioelectronic Sensors," ACS Nano, Nov. 2020. [[http://doi.org/10.1021/acsnano.0c08622|DOI]]
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 +  * E. Chai, M. Pilanci and B. Murmann, "Separating the Effects of Batch Normalization on CNN Training Speed and Stability Using Classical Adaptive Filter Theory," Asilomar Conference on Signals, Systems, and Computers, Nov. 2020, pp. 1214-1221. [[http://doi.org/10.1109/IEEECONF51394.2020.9443275|DOI]]
    
   * D.M. Stipanović, M.N. Kapetina, M.R. Rapaić, and B. Murmann, "Stability of Gated Recurrent Unit Neural Networks: Convex Combination Formulation Approach," J. Optim. Theory Appl., Nov. 2020. [[http://doi.org/10.1007/s10957-020-01776-w|DOI]]   * D.M. Stipanović, M.N. Kapetina, M.R. Rapaić, and B. Murmann, "Stability of Gated Recurrent Unit Neural Networks: Convex Combination Formulation Approach," J. Optim. Theory Appl., Nov. 2020. [[http://doi.org/10.1007/s10957-020-01776-w|DOI]]
          
-  * Wei-Hsiang Ho, Yi-Hsun Hsieh, B. Murmann, and Wei-Zen Chen, "A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4[[http://dx.doi.org/10.1109/ISCAS45731.2020.9180483|DOI]]+  * Wei-Hsiang Ho, Yi-Hsun Hsieh, B. Murmann, and Wei-Zen Chen, "A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4[[http://dx.doi.org/10.1109/ISCAS45731.2020.9180483|DOI]]
  
   * S. Weinreich, D. Muratore, Y. Chae, T. McKay, and B. Murmann, "Implications of Finite Clock Transition Time for LPTV Circuit Analysis," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4. [[http://dx.doi.org/10.1109/ISCAS45731.2020.9180691|DOI]]   * S. Weinreich, D. Muratore, Y. Chae, T. McKay, and B. Murmann, "Implications of Finite Clock Transition Time for LPTV Circuit Analysis," Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Oct. 2020, pp. 1-4. [[http://dx.doi.org/10.1109/ISCAS45731.2020.9180691|DOI]]
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   * G. Nyikayaramba and B. Murmann, "S-Parameter-Based Defect Localization for Ultrasonic Guided Wave SHM," Aerospace, vol. 7, no. 3, 2020. [[http://dx.doi.org/10.3390/aerospace7030033|DOI]]   * G. Nyikayaramba and B. Murmann, "S-Parameter-Based Defect Localization for Ultrasonic Guided Wave SHM," Aerospace, vol. 7, no. 3, 2020. [[http://dx.doi.org/10.3390/aerospace7030033|DOI]]
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-  * E. Chai, M. Pilanci, and B. Murmann, “Separating the Effects of Batch Normalization on CNN Training Speed and Stability Using Classical Adaptive Filter Theory,” arXiv:2002.10674 [cs.NE], Feb. 2020. [[http://arxiv.org/abs/2002.10674|URL]] 
  
   * O. Mattia and B. Murmann, "An 80 GS/s 5.5 ENOB Time-Interleaved Inverter-Based CMOS Track-and-Hold," Electronics Letters, Jan. 2020. [[http://dx.doi.org/10.1049/el.2019.4104|DOI]]   * O. Mattia and B. Murmann, "An 80 GS/s 5.5 ENOB Time-Interleaved Inverter-Based CMOS Track-and-Hold," Electronics Letters, Jan. 2020. [[http://dx.doi.org/10.1049/el.2019.4104|DOI]]
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   * D. Bankman, L. Yang, B. Moons, M. Verhelst and B. Murmann, "An Always-On 3.8μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28nm CMOS," ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2018, pp. 222-223. [[http://dx.doi.org/10.1109/ISSCC.2018.8310264]]    * D. Bankman, L. Yang, B. Moons, M. Verhelst and B. Murmann, "An Always-On 3.8μJ/86% CIFAR-10 Mixed-Signal Binary CNN Processor with All Memory on Chip in 28nm CMOS," ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2018, pp. 222-223. [[http://dx.doi.org/10.1109/ISSCC.2018.8310264]] 
      
-  * K. Zheng, B. Murmann, H. Zhang and G. Zhang, "Feedforward Equalizer Location Study for High Speed Serial Systems," DesingCon, Santa Clara, CA, Jan. 2018. [[http://designcon.com/paper-award-winners]] **Best Paper Award.** +  * K. Zheng, B. Murmann, H. Zhang and G. Zhang, "Feedforward Equalizer Location Study for High Speed Serial Systems," DesingCon, Santa Clara, CA, Jan. 2018. [[http://designcon.com/paper-award-winners]] **Best Paper Award** 
  
 ====== 2017  ====== ====== 2017  ======
   * M-C. Chen, A. Peña Perez, S-R. Kothapalli, P. Cathelin, A. Cathelin, S.S. Gambhir, and B. Murmann, "A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI," IEEE J. Solid-State Circuits, vol. 52, no. 11, pp. 2843-2856, Nov. 2017. [[http://dx.doi.org/10.1109/JSSC.2017.2749425]]    * M-C. Chen, A. Peña Perez, S-R. Kothapalli, P. Cathelin, A. Cathelin, S.S. Gambhir, and B. Murmann, "A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI," IEEE J. Solid-State Circuits, vol. 52, no. 11, pp. 2843-2856, Nov. 2017. [[http://dx.doi.org/10.1109/JSSC.2017.2749425]] 
      
-  * U. Kraft, F. Molina-Lopez, C. Zhu, Y. Wang, Z. Bao and B. Murmann, "Inkjet-printed, intrinsically stretchable conductors and interconnects," Proc. SPIE Organic Photonics + Electronics, San Diego, CA, Aug. 2017. [[http://dx.doi.org/10.1117/12.2274583]] +  * U. Kraft, F. Molina-Lopez, C. Zhu, Y. Wang, Z. Bao and B. Murmann, "Inkjet-printed, intrinsically stretchable conductors and interconnects," Proc. SPIE Organic Photonics + Electronics, San Diego, CA, Aug. 2017. [[http://dx.doi.org/10.1117/12.2274583]] 
 + 
 +  * C. Gupta, R.M. Walker, S. Chang, S.R. Fischer, M. Seal, B. Murmann, and R.T. Howe, "Quantum Tunneling Currents in a Nanoengineered Electrochemical System," Journal of Physical Chemistry C, 121 (28), pp. 15085-15105, Jul. 2017. [[http://dx.doi.org/10.1021/acs.jpcc.7b04350]]
      
   * A. Chortos, C. Zhu, J.Y. Oh, X. Yan, I. Pochorovski, J.W.F. To, N. Liu, U. Kraft, B. Murmann, and Z. Bao, "Investigating Limiting Factors in Stretchable All-Carbon Transistors for Reliable Stretchable Electronics," ACS Nano, Jul. 2017. [[http://dx.doi.org/10.1021/acsnano.7b02458]]    * A. Chortos, C. Zhu, J.Y. Oh, X. Yan, I. Pochorovski, J.W.F. To, N. Liu, U. Kraft, B. Murmann, and Z. Bao, "Investigating Limiting Factors in Stretchable All-Carbon Transistors for Reliable Stretchable Electronics," ACS Nano, Jul. 2017. [[http://dx.doi.org/10.1021/acsnano.7b02458]] 
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   * P. Nikaeen and B. Murmann, “Digital correction of dynamic track-and-hold errors providing SFDR > 83 dB up to fin = 470 MHz,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 161-164. [[http://dx.doi.org/10.1109/CICC.2008.4672048]]    * P. Nikaeen and B. Murmann, “Digital correction of dynamic track-and-hold errors providing SFDR > 83 dB up to fin = 470 MHz,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 161-164. [[http://dx.doi.org/10.1109/CICC.2008.4672048]] 
      
-  * B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 105-112. [[http://dx.doi.org/10.1109/CICC.2008.4672032]]    * Best Invited Paper Award.    *  +  * B. Murmann, “A/D converter trends: Power dissipation, scaling and digitally assisted architectures,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, Sep. 2008, pp. 105-112. [[http://dx.doi.org/10.1109/CICC.2008.4672032]]   **Best Invited Paper Award**  
      
-  * J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2008, pp. 216-217. [[http://dx.doi.org/10.1109/VLSIC.2008.4586012]]    * Best Student Paper Award.     +  * J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification,” in Symp. VLSI Circuits Dig., Honolulu, HI, Jun. 2008, pp. 216-217. [[http://dx.doi.org/10.1109/VLSIC.2008.4586012]]   **Best Student Paper Award** 
      
   * B. Murmann, C. Vogel, and H. Koeppl, “Digitally enhanced analog circuits: System aspects,” in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 2008, pp. 560-563. [[http://dx.doi.org/10.1109/ISCAS.2008.4541479]]    * B. Murmann, C. Vogel, and H. Koeppl, “Digitally enhanced analog circuits: System aspects,” in Proc. IEEE Int. Symp. Circuits Syst., Seattle, WA, May 2008, pp. 560-563. [[http://dx.doi.org/10.1109/ISCAS.2008.4541479]] 
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 ====== Books and Book Chapters  ====== ====== Books and Book Chapters  ======
 +
 +  * B. Murmann, "Mixed-Signal Compute and Memory Fabrics for Deep Neural Networks," in Analog Circuits for Machine Learning, Current/Voltage/Temperature Sensors, and High-speed Communication, by P. Harpe, K.A. Makinwa, and A. Baschirotto (eds), Springer, Cham, 2022. [[http://doi.org/10.1007/978-3-030-91741-8_1|DOI]]
  
   * B. Murmann and B. Hoefflinger (eds.), "NANO-CHIPS 2030: On-Chip AI for an Efficient Data-Driven World," Springer, 2020. [[http://dx.doi.org/10.1007/978-3-030-18338-7|DOI]]   * B. Murmann and B. Hoefflinger (eds.), "NANO-CHIPS 2030: On-Chip AI for an Efficient Data-Driven World," Springer, 2020. [[http://dx.doi.org/10.1007/978-3-030-18338-7|DOI]]
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 ====== Patents  ====== ====== Patents  ======
 +
 +  * B. Murmann and D.A. Villamizar, "N-path Spectral Decomposition in Acoustic Signals," US20210134307A1. [[https://patents.google.com/patent/US20210134307A1/|WWW]]
 +
   * B. Murmann, D.G. Muratore, E.J. Chichilnisky, P. Tandon, "Data-compressive sensor array," WO2020082081A1. [[https://patents.google.com/patent/WO2020082081A1/|WWW]]    * B. Murmann, D.G. Muratore, E.J. Chichilnisky, P. Tandon, "Data-compressive sensor array," WO2020082081A1. [[https://patents.google.com/patent/WO2020082081A1/|WWW]] 
  
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   * E. Iroaga and B. Murmann, "Method and system for driver circuits of capacitive loads," US 7369080, May 6, 2008. [[https://patents.google.com/patent/US7369080B1|WWW]]   * E. Iroaga and B. Murmann, "Method and system for driver circuits of capacitive loads," US 7369080, May 6, 2008. [[https://patents.google.com/patent/US7369080B1|WWW]]
 ====== PhD Theses  ====== ====== PhD Theses  ======
 +  * G. Nyikayaramba, "Enabling low voltage electronics for ultrasonic structural health monitoring," 2023 [[https://searchworks.stanford.edu/view/in00000001244]]
 +  
 +  * Q. Lu, "TinyML computer vision using coarsely-quantized log-gradient input images," 2023 [[https://searchworks.stanford.edu/view/14801748]]
 +
 +  * S. Weinreich, "Linear periodically time-varying circuits for the Internet of Everything," 2022 [[https://searchworks.stanford.edu/view/14310526]]
 +
 +  * V. Kesler, "Bioelectronic interfaces for molecular quantification," 2022 [[https://searchworks.stanford.edu/view/14233969]]
 +
 +  * P. Caragiulo, "High-speed D/A conversion in FinFET CMOS technology," 2022 [[https://searchworks.stanford.edu/view/14229453]]
 +
 +  * E. Chai, "Analysis of quantization and normalization effects in deep neural networks," 2021 [[http://searchworks.stanford.edu/view/13971425]]
 +
 +  * A. Gural, "Algorithmic Techniques for Neural Network Training on Memory-Constrained Hardware," 2021 [[http://searchworks.stanford.edu/view/13972036]]
 +
 +  * D. Villamizar, "Low power audio feature extraction for machine learning applications," 2021 [[http://searchworks.stanford.edu/view/13964971]]
 +
 +  * P.-H. Wei, "Layout automation for analog and mixed-signal circuits using digital place-and-route tools," 2021 [[http://searchworks.stanford.edu/view/13876458]]
 +
   * N. Hammler, "Sub-Nyquist Receiver for Digital Predistortion of RF Power Amplifiers," 2019 [[http://purl.stanford.edu/kw638wk0205]]   * N. Hammler, "Sub-Nyquist Receiver for Digital Predistortion of RF Power Amplifiers," 2019 [[http://purl.stanford.edu/kw638wk0205]]