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po-hsuan_wei [2020/11/04 12:39]
pohsuan [Layout is the Bottleneck of Analog and Mixed-Signal (AMS) Designs]
po-hsuan_wei [2020/11/04 12:42]
pohsuan [Po-Hsuan Wei]
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 ====== Po-Hsuan Wei ====== ====== Po-Hsuan Wei ======
 +~~NOTOC~~
 {{wiki:Headshot_PHW.jpg?320x214|Headshot_PHW.jpg}} {{wiki:Headshot_PHW.jpg?320x214|Headshot_PHW.jpg}}
  
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 {{wiki:Research Profile Figures PHW 20170720.png?800x374|Research Profile Figures PHW 20170720.png}}  {{wiki:Research Profile Figures PHW 20170720.png?800x374|Research Profile Figures PHW 20170720.png}} 
  
-Figure 1. Explosion of Design Rules [[3]];Figure 2. Proposed Automated Layout Generation Flow for AMS Circuits +Figure 1. Explosion of Design Rules [3] Figure 2. Proposed Automated Layout Generation Flow for AMS Circuits 
  
 [1] P. Kinget, "Designing analog and RF circuits in nanoscale CMOS technologies: Scale the supply, reduce the area and use digital gates", Proc. IEEE Int. Conf. Microwaves, Communications, Antennas and Electronics Systems, pp. 1, 2009 \\  [1] P. Kinget, "Designing analog and RF circuits in nanoscale CMOS technologies: Scale the supply, reduce the area and use digital gates", Proc. IEEE Int. Conf. Microwaves, Communications, Antennas and Electronics Systems, pp. 1, 2009 \\ 
 [2] K. -W. Su, Y. -M. Sheu, C. -K. Lin, S. -J. Yang, W. -J. Liang, X. Xi, C. -S. Chiang, J. -K. Her, Y. -T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” 2003, pp. 245–248. \\ [2] K. -W. Su, Y. -M. Sheu, C. -K. Lin, S. -J. Yang, W. -J. Liang, X. Xi, C. -S. Chiang, J. -K. Her, Y. -T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics,” 2003, pp. 245–248. \\
 [3] http://www.electronicdesign.com/eda/are-you-really-ready-your-next-node [3] http://www.electronicdesign.com/eda/are-you-really-ready-your-next-node