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po-hsuan_wei [2020/11/04 12:39] – [Layout is the Bottleneck of Analog and Mixed-Signal (AMS) Designs] pohsuan | po-hsuan_wei [2020/11/04 12:42] – [Po-Hsuan Wei] pohsuan | ||
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====== Po-Hsuan Wei ====== | ====== Po-Hsuan Wei ====== | ||
+ | ~~NOTOC~~ | ||
{{wiki: | {{wiki: | ||
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- | Figure 1. Explosion of Design Rules [[3]];Figure 2. Proposed Automated Layout Generation Flow for AMS Circuits | + | Figure 1. Explosion of Design Rules [3] Figure 2. Proposed Automated Layout Generation Flow for AMS Circuits |
[1] P. Kinget, " | [1] P. Kinget, " | ||
[2] K. -W. Su, Y. -M. Sheu, C. -K. Lin, S. -J. Yang, W. -J. Liang, X. Xi, C. -S. Chiang, J. -K. Her, Y. -T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics, | [2] K. -W. Su, Y. -M. Sheu, C. -K. Lin, S. -J. Yang, W. -J. Liang, X. Xi, C. -S. Chiang, J. -K. Her, Y. -T. Chia, C. H. Diaz, and C. Hu, “A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics, | ||
[3] http:// | [3] http:// |