Hussein_Ali
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<span style=“color: rgb(153, 51, 102);”>SHORT BIO</span><br>
received the B.Sc. and M.Sc. degrees from Ain Shams University, Cairo, Egypt in 2006 and 2010 respectively, and the PH.D. degree from Universite Pierre et Marie Curie, Sorbonne Universites, Paris, France in 2013, all in electrical engineering. From 2006 to 2009, he was an analog design engineer in Si-Ware Systems. From 2009, he joined LIP6/UPMC, where he worked on digitally assisted high speed ADCs. From 2014, he is a postdoctoral research fellow in Murmann Mixed-Signal Group at Stanford University, Stanford, CA.<br>
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<span style=“color: rgb(153, 51, 102);”>PROJECT</span>
*Circuit Design in FinFET Technology
CMOS technology scaling is continuing to provide more power efficient and higher speed systems and circuits in a smaller die area. However, scaling below 100 nm starts to face significant issues related to leakage, lower device gain and other short channel effects, which jeopardizes the cost-benefit of the technology scaling. FinFET technology is introduced by the semiconductor industry in order to solve the challenges facing the conventional planar CMOS in deep submicron technologies. While the FinFET transistor gives more control to the gate on the channel, leading to less leakage and higher device intrinsic gain, its 3D structure makes the associated parasitics more significant than the planar CMOS processes. One design practice would be to exploit the enhanced transistor gain and not only depending on the speed gain of the technology minimum feature size to overcome the extra device parasitics and achieve an optimum power-efficient design. An 8-bit 800 MS/s SAR ADC testchip is designed in 14 nm FinFET technology and it achieves a FOM of 33 fJ/conv-step from post-layout results. The learning from this initial prototype would result in a higher speed converter.
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