====== Wiki Page ======

**Cadence Software at Stanford University** 

**Cadence University Program Member** 

**List of Cadence Software Available** 
  

  * Virtuoso Design Environment
    - Schematic Editor
    - Layout
    - ADE 

  * Circuit Simulation
    - Spectre 

  * Physical Verification
    - Quantus QRC
    - Physical Verification System 

  * Design for Manufacturing
    - Voltus 

  * Signal Integrity
    - Tempus 

  * Digital Implementation
    - Innovus
    - Encounter
    - Virtuoso Digital Implementation 

  * Test
    - Modus 

  * Formal Verification
    - Conformal 

  * JasperGold Formal Verification Platform 
  * Synthesis
    - Genus
    - Stratus HLS 

  * PCB Design and Verification
    - Allegero 

  * Incisive 
  * Liberate

**Research Groups Using Cadence Tools**


[[http://vlsiweb.stanford.edu/|Horowitz Group]] 

[[http://www-smirc.stanford.edu/|Tom Lee Group]] 

[[https://profiles.stanford.edu/s-simon-wong?tab=bio|Simon Wong Group]] 

[[https://www.stanford.edu/group/murmann_group/cgi-bin/mediawiki/index.php/Main_Page|Murmann Group]] 

[[http://biosystems.stanford.edu/|Ada Poon Group]] 

[[http://cgi.stanford.edu/~group-rsg_csl/twiki/bin/view.pl/Public/WebHome|Mitra Group]] 

[[http://cva.stanford.edu/|Dally Group]] 

[[https://arbabianlab.stanford.edu/|Arbabian Group]] 

**Courses Using Cadence Tools** 

[[http://scpd.stanford.edu/search/publicCourseSearchDetails.do?method=load&courseId=36675253|EE213 Digital MOS Integrated Circuits]] 

[[http://scpd.stanford.edu/search/publicCourseSearchDetails.do?method=load&courseId=15912639|EE314A RF Integrated Circuit Design]] 

[[http://scpd.stanford.edu/search/publicCourseSearchDetails.do?method=load&courseId=18505704|EE314B Advanced RF Integrated Circuit Design]] 

[[http://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures.html|EE371 Advanced VLSI Circuit Design]] 

[[https://canvas.stanford.edu/courses/47524/|EE315 Analog-Digital Interface Circuits]] 

[[https://cadwiki.stanford.edu/mediawiki/index.php/Main_Page|Cadence Tool Help at Stanford]] 

Information is provided 'as is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions. Keep your master intact until you are satisfied with the use of this information within your environment. 

Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134 

Last Modified: 11/26/2018

Webpage Maintained By: Daniel Villamizar (email: danvilla AT stanford DOT edu)